EPM5032DI-20 vs EPM5032DC-25 Pengandingan

Pengandingan Sisi Kiri Sisi Kanan Terperinci EPM5032DI-20 disebabkan oleh Intel dan EPM5032DC-25 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.

Pengandingan Spesifikasi

Parametr EPM5032DI-20 EPM5032DC-25
Merek Intel Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Obsolete NRND
Family MAX 5000 (Altera legacy EPLD) —
Architecture CMOS PAL-type EPLD with PIA PAL-Type, Single-LAB, 32-Macrocell
Macrocells 32 32
Dedicated Inputs 7 —
Bidirectional I/O Pins 16 —
Product Terms 320 (maximum) —
Flip-Flops 16 (one per macrocell) —
Frekuensi Klock Maksimum 62.5 MHz —
Pin-to-Pin Delay 20 ns (speed grade -20) —
Kemasan Ceramic DIP-20 (windowed, UV-erasable) CDIP-28 (Windowed Ceramic DIP-28)
Suhu Operasi Industrial (per 'I' suffix) [DATA_NEEDED: operating temperature range]
Programming UV-erasable CMOS, JEDEC fuse file —
Development Tool Altera MAX+PLUS II (legacy) —
Status RoHS [DATA_NEEDED: RoHS compliance status for ceramic DIP variant] Lead Free / RoHS Compliant (per distributor listings)
Lead-Free [DATA_NEEDED: lead-free status] —
Manufacturer — Altera (Intel Programmable Solutions Group)
Product Family — MAX 5000
Device Type — UV Erasable Programmable Logic Device (EPLD)
Pin-to-Pin Propagation Delay (tPD) — 25 ns
Maximum Counter Frequency (fCNT) — [DATA_NEEDED: maximum counter frequency]
Setup Time (tSU) — [DATA_NEEDED: setup time]
Number of Dedicated Inputs — 32 (in DIP-28 pinout)
Number of I/O Pins — 22 (in DIP-28 pinout, 4 used as dedicated inputs)
Process Technology — CMOS, EPROM (UV-Erasable)
Output Structure — Programmable I/O with output enable
Flip-Flop Configuration — D, T, JK, or SR (programmable)
Programming Method — UV erase + Altera/Intel MAX+PLUS II programmer
Erasure Method — UV light through ceramic window

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