EPM5032JC25 vs EPM5016DC-20 Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EPM5032JC25 disebabkan oleh Altera dan EPM5016DC-20 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Pengandingan Spesifikasi
| Parametr | EPM5032JC25 | EPM5016DC-20 |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | Obsolete |
| Family | MAX 5000 | MAX 5000 |
| Device | EPM5032 | — |
| Logic Elements | 32 macrocells | — |
| Propagation Delay (tPD) | 25 ns | 20 ns |
| Maximum Internal Frequency | 62.5 MHz | — |
| Product Terms | 320 | 160 |
| Flip-Flops | 32 | — |
| Dedicated Inputs | 7 | 7 |
| Bidirectional I/O Pins | 16 | — |
| Total Inputs to Array | 24 | — |
| Bilangan Output | 16 | — |
| Architecture | PAL-type macrocells with global Programmable Interconnect Array (PIA) | PAL-type macrocell with Programmable Interconnect Array (PIA) |
| Technology | CMOS EPROM, UV-erasable (windowed) / OTP | — |
| Tegangan Pemberi Arus | 5 V (TTL-level I/O) | — |
| Kemasan | 28-pin PLCC (JC) | — |
| Jenis Pemasangan | Surface Mount | — |
| Status RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance] |
| Device Type | — | EPLD (UV-Erasable Programmable Logic Device) |
| Macrocells | — | 16 |
| I/O Pins | — | 8 |
| Frekuensi Klock Maksimum | — | 62.5 MHz |
| Maximum Supply Voltage | — | 5.25 V |
| Nominal Supply Voltage | — | 5.0 V |
| Process Technology | — | CMOS, UV-erasable |
| Package Type | — | 20-pin Ceramic DIP (Cerdip) with UV window |
| Package Suffix Code | — | DC = Ceramic DIP, Commercial |
| Speed Grade | — | -20 = 20 ns tPD |
| Suhu Operasi | — | [DATA_NEEDED: operating temperature range] |
| Programming Method | — | UV erase + EPROM-style programming via Altera programming hardware |