EPM5128GC-1 vs EPM5128JC Pengandingan

Pengandingan Sisi Kiri Sisi Kanan Terperinci EPM5128GC-1 disebabkan oleh Altera dan EPM5128JC disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.

Pengandingan Spesifikasi

Parametr EPM5128GC-1 EPM5128JC
Merek Altera Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Obsolete Obsolete
Family MAX 5000 —
Device Type UV-erasable CMOS CPLD EPLD / CPLD
Macrocells 128 —
Usable Gates 2,500 —
Dedicated Inputs 7 8
Maximum User I/O Pins 52 —
Nominal Supply Voltage 5 V —
Supply Voltage Range 4.75 V to 5.25 V —
Maximum Operating Frequency 62.5 MHz —
Propagation Delay (tPD) 16 ns (typical, -1 speed grade) 35 ns
Kemasan PGA-96+ (Pin Grid Array, ceramic windowed) —
Technology CMOS, UV-erasable EPROM —
Suhu Operasi -40C to +85C (industrial) Commercial 0C to +70C
IOL / IOH 100 mA / 25 mA per pin (legacy figure, [DATA_NEEDED: verify exact drive spec]) —
Security Bit Programmable, prevents readback —
Programming Method UV erase + EPROM program (or device programmer) —
Aras MSL [DATA_NEEDED: MSL level] —
Status RoHS [DATA_NEEDED: RoHS compliance - ceramic PGA part is legacy] [DATA_NEEDED: RoHS status - legacy part]
Product Family — MAX 5000
Macrocell Count — 128
Logic Elements — Programmable AND/OR/XOR array
Supply Voltage (VCC) — 5 V (typical)
Bilangan Pin — 68
Package Type — PLCC-68 (JLCC) ceramic, J-leaded
User I/O Pins — [DATA_NEEDED: user I/O pin count]
Configuration Memory — UV-erasable EPROM (windowed package)
Programming Interface — Altera MAX+PLUS II / A+PLUS / legacy programmer
Jenis Pemasangan — Surface Mount (PLCC socket or solder)
Boundary Scan — JTAG IEEE 1149.1 (family feature)
Process Technology — CMOS EPROM
Lead-Free — [DATA_NEEDED: lead-free status]

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