EPM5128JC vs EPM5128LC2 Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EPM5128JC disebabkan oleh Altera dan EPM5128LC2 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Altera
EPM5128LC2 - 128-Macrocell MAX 5000 CPLD, 45ns, 5V | Altera
EPM5128LC2 ⚠ Bahagian terakhir untuk beliPengandingan Spesifikasi
| Parametr | EPM5128JC | EPM5128LC2 |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | Masa Terakhir Dibeli |
| Product Family | MAX 5000 | — |
| Device Type | EPLD / CPLD | CPLD (Complex Programmable Logic Device) |
| Macrocell Count | 128 | — |
| Propagation Delay (tPD) | 35 ns | 45 ns |
| Logic Elements | Programmable AND/OR/XOR array | — |
| Supply Voltage (VCC) | 5 V (typical) | 5 V |
| Bilangan Pin | 68 | — |
| Package Type | PLCC-68 (JLCC) ceramic, J-leaded | — |
| Dedicated Inputs | 8 | — |
| User I/O Pins | [DATA_NEEDED: user I/O pin count] | — |
| Configuration Memory | UV-erasable EPROM (windowed package) | On-chip EPROM (non-volatile) |
| Programming Interface | Altera MAX+PLUS II / A+PLUS / legacy programmer | — |
| Suhu Operasi | Commercial 0C to +70C | -40 C to +85 C (extended commercial) |
| Jenis Pemasangan | Surface Mount (PLCC socket or solder) | Through-Hole / Socketed |
| Boundary Scan | JTAG IEEE 1149.1 (family feature) | JTAG / IEEE 1149.1 |
| Process Technology | CMOS EPROM | CMOS EPROM |
| Status RoHS | [DATA_NEEDED: RoHS status - legacy part] | [DATA_NEEDED: RoHS status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Family | — | MAX 5000 |
| Macrocells | — | 128 |
| Logic Array Blocks (LABs) | — | 8 |
| Interconnect | — | Programmable Interconnect Array (PIA) |
| Global Clock Inputs | — | 1 dedicated |
| Kemasan | — | PGA (Pin Grid Array, ceramic) |