EPM5192JC-1 vs EPM5192JC1 Pengandingan

Pengandingan Sisi Kiri Sisi Kanan Terperinci EPM5192JC-1 disebabkan oleh Altera dan EPM5192JC1 disebabkan oleh Intel. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.

Pengandingan Spesifikasi

Parametr EPM5192JC-1 EPM5192JC1
Merek Altera Intel
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Obsolete Obsolete
Family MAX 5000 MAX 5000 (MAX 5xxx CPLD)
Device Type CPLD - Complex Programmable Logic Device —
Technology CMOS, UV-Erasable / OTP —
Macrocells 192 —
Usable Gates 3750 3750
Propagation Delay (tPD) 40 ns (speed grade -1) —
Maximum Internal Frequency (fMAX) 62.5 MHz —
Supply Voltage (VCC) 4.75 V to 5.25 V 5 V (nominal)
User I/O Pins 84 —
Package Type 84-pin Ceramic Quad Flat Pack (CQFP), windowed —
JEDEC Package Code S-CQCC-J84 —
Suhu Operasi 0 C to +70 C (commercial) [DATA_NEEDED: operating temp range]
Configuration Memory UV-EPROM (erasable under UV lamp) —
Programming Interface Altera MAX programming interface (parallel, pre-JTAG for this family) JTAG-compatible (Altera MAX 5xxx)
Process CMOS EPROM —
I/O Standard TTL/CMOS 5 V compatible —
Manufacturer — Intel (formerly Altera Corporation)
Macro Cells — 192
Maximum Operating Frequency — 62.5 MHz
Process Technology — 0.5 µm CMOS, UV-erasable EPROM
Propagation Delay (typ) — [DATA_NEEDED: propagation delay in ns]
I/O Pins — [DATA_NEEDED: I/O pin count]
Kemasan — [DATA_NEEDED: exact package from datasheet]
Jenis Pemasangan — [DATA_NEEDED: surface mount or through-hole]
Logic Blocks (LABs) — 24 (8 macrocells per LAB)
Status RoHS — unknown
AEC-Q100 — not_applicable
Lifecycle — Obsolete - last-time-buy stock only at franchised distributors

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