EPM5192LC1 vs EPM5192LC-25 Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EPM5192LC1 disebabkan oleh Altera dan EPM5192LC-25 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Pengandingan Spesifikasi
| Parametr | EPM5192LC1 | EPM5192LC-25 |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | Obsolete |
| Family | MAX 5000 | MAX 5000 |
| Device Type | Complex PLD (CPLD), UV-erasable/OTP | — |
| Macrocells | 192 | 192 |
| Equivalent Gates | 3750 | — |
| Dedicated Inputs | 7 | — |
| User I/O Pins | 64 | — |
| Kemasan | PQCC-84 (JEDEC S-PQCC-J84, 84-lead Plastic Leaded Chip Carrier) | JLCC-84 (ceramic J-lead chip carrier) |
| Nominal Supply Voltage (VCC) | 5 V | — |
| Supply Voltage Range | 4.75 V to 5.25 V | — |
| Frekuensi Klock Maksimum | 50 MHz | — |
| Propagation Delay (tPD) | 40 ns | — |
| Process Technology | CMOS EPROM | — |
| Programming Method | OTP (LC plastic package); UV-erasable equivalents in JC ceramic package | — |
| Operating Temperature (Commercial 'LC') | 0 °C to 70 °C | — |
| Jenis Pemasangan | Surface Mount | Surface Mount |
| Status RoHS | [DATA_NEEDED: RoHS status] | Unknown (legacy ceramic package typically non-RoHS) |
| JEDEC Package Code | S-PQCC-J84 | — |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Logic Elements | — | 192 (1 macrocell ≈ 1 LE in MAX 5000 architecture) |
| Pin-to-Pin Delay (tPD) | — | 25 ns |
| Speed Grade | — | -25 (25 ns) |
| Programmable Technology | — | UV-erasable / OTP (EPROM-based) |
| Programming Interface | — | JTAG / Altera programming hardware (legacy) |
| Suhu Operasi | — | 0C to +70C (commercial) |
| Tegangan Pemberi Arus | — | 5 V (typical, MAX 5000) |
| I/O Standard | — | TTL-compatible |
| Configuration Memory | — | Non-volatile EPROM (on-chip) |
| Manufacturer | — | Altera Corporation (now Intel PSG) |