EPM7096LC84-15 vs EPM7096QC100-10 Pengandingan

Pengandingan Sisi Kiri Sisi Kanan Terperinci EPM7096LC84-15 disebabkan oleh Altera dan EPM7096QC100-10 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.

Pengandingan Spesifikasi

Parametr EPM7096LC84-15 EPM7096QC100-10
Merek Altera Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Obsolete Obsolete
Family MAX 7000 MAX 7000
Series MAX 7000 (second-generation MAX architecture) —
Macro Cells 96 —
Logic Array Blocks (LABs) 4 —
Usable Gates 1,800 —
Pin-to-Pin Propagation Delay (tPD) 15 ns —
Maximum Operating Frequency 76.9 MHz 100 MHz
User I/O Pins 68 (36 per LAB, [DATA_NEEDED: exact LAB-level split]) 76
Supply Voltage (VCC) 4.75 V to 5.25 V 4.75 V to 5.25 V
Programmable Type EE PLD (in-system programmable via JTAG) —
Programming Interface IEEE Std. 1149.1 JTAG ByteBlaster / parallel (JTAG ISP on MAX 7000S variants)
Suhu Operasi 0C to +70C (commercial) 0 °C to +70 °C (commercial)
Kemasan / Case 84-PLCC (J-Lead) —
Supplier Device Package 84-PLCC (29.31 x 29.31 mm) —
Jenis Pemasangan Surface Mount Surface Mount
Data Retention [DATA_NEEDED: data retention years] —
Erase/Program Endurance [DATA_NEEDED: erase/program cycle count] —
Status RoHS [DATA_NEEDED: RoHS compliance status] [DATA_NEEDED: RoHS compliance status]
Macrocells — 96
Logic Array Blocks — 4
Propagation Delay (tPD) — 10 ns
Technology — EEPROM-based CMOS
Boundary Scan — IEEE Std. 1149.1 (JTAG) on MAX 7000S
PCI Compliance — Yes (PCI SIG Local Bus Specification Rev. 2.2 at -10 speed grade)
Kemasan — 100-pin PQFP (R-PQFP-G100, 20×14 mm, 0.65 mm pitch)

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