EPM7096QC100-10 vs EPM7096LC68-15 Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EPM7096QC100-10 disebabkan oleh Altera dan EPM7096LC68-15 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Altera
EPM7096QC100-10 - 96-Macrocell MAX 7000 CPLD, 10ns, PQFP-100 | Altera
EPM7096QC100-10 Obsolete
Pengandingan Spesifikasi
| Parametr | EPM7096QC100-10 | EPM7096LC68-15 |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | NRND |
| Family | MAX 7000 | MAX 7000 |
| Macrocells | 96 | 96 |
| Logic Array Blocks | 4 | — |
| User I/O Pins | 76 | 52 |
| Propagation Delay (tPD) | 10 ns | 15 ns |
| Maximum Operating Frequency | 100 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | — |
| Technology | EEPROM-based CMOS | — |
| Programming Interface | ByteBlaster / parallel (JTAG ISP on MAX 7000S variants) | — |
| Boundary Scan | IEEE Std. 1149.1 (JTAG) on MAX 7000S | — |
| PCI Compliance | Yes (PCI SIG Local Bus Specification Rev. 2.2 at -10 speed grade) | — |
| Suhu Operasi | 0 °C to +70 °C (commercial) | 0C to +70C (commercial) |
| Kemasan | 100-pin PQFP (R-PQFP-G100, 20×14 mm, 0.65 mm pitch) | PLCC-68 (LC68) |
| Jenis Pemasangan | Surface Mount | Surface Mount (PLCC socket compatible) |
| Status RoHS | [DATA_NEEDED: RoHS compliance status] | — |
| Logic Array Blocks (LABs) | — | 4 |
| Supply Voltage (VCCINT/VCCIO) | — | 4.75 V to 5.25 V (5 V nominal) |
| Programmable Technology | — | EEPROM (second-generation MAX architecture) |
| In-System Programming | — | Yes (IEEE 1149.1 JTAG) |
| Logic Gates (typical) | — | 1800 gates |
| Memory Bits | — | Non-volatile configuration, 100 erase/program cycles per macrocell |
| Lead-Free / RoHS | — | Compliant per Altera product page |
| Programming Tool Support | — | Altera MAX+PLUS II, Quartus II; ByteBlaster / ByteBlasterMV |