EPM7096QC100-10 vs EPM7096LC68-15 Comparison
Detailed side-by-side comparison of EPM7096QC100-10 by Altera and EPM7096LC68-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM7096QC100-10 - 96-Macrocell MAX 7000 CPLD, 10ns, PQFP-100 | Altera
EPM7096QC100-10 Obsolete
Specification Comparison
| Parameter | EPM7096QC100-10 | EPM7096LC68-15 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $7.10 | $7.20 |
| Family | MAX 7000 | MAX 7000 |
| Macrocells | 96 | 96 |
| Logic Array Blocks | 4 | β |
| User I/O Pins | 76 | 52 |
| Propagation Delay (tPD) | 10 ns | 15 ns |
| Maximum Operating Frequency | 100 MHz | β |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | β |
| Technology | EEPROM-based CMOS | β |
| Programming Interface | ByteBlaster / parallel (JTAG ISP on MAX 7000S variants) | β |
| Boundary Scan | IEEE Std. 1149.1 (JTAG) on MAX 7000S | β |
| PCI Compliance | Yes (PCI SIG Local Bus Specification Rev. 2.2 at -10 speed grade) | β |
| Operating Temperature | 0 Β°C to +70 Β°C (commercial) | 0C to +70C (commercial) |
| Package | 100-pin PQFP (R-PQFP-G100, 20Γ14 mm, 0.65 mm pitch) | PLCC-68 (LC68) |
| Mounting Type | Surface Mount | Surface Mount (PLCC socket compatible) |
| RoHS Status | [DATA_NEEDED: RoHS compliance status] | β |
| Logic Array Blocks (LABs) | β | 4 |
| Supply Voltage (VCCINT/VCCIO) | β | 4.75 V to 5.25 V (5 V nominal) |
| Programmable Technology | β | EEPROM (second-generation MAX architecture) |
| In-System Programming | β | Yes (IEEE 1149.1 JTAG) |
| Logic Gates (typical) | β | 1800 gates |
| Memory Bits | β | Non-volatile configuration, 100 erase/program cycles per macrocell |
| Lead-Free / RoHS | β | Compliant per Altera product page |
| Programming Tool Support | β | Altera MAX+PLUS II, Quartus II; ByteBlaster / ByteBlasterMV |