EPM7128STC100-15N vs EPM7128SQC100-10N Pengandingan

Pengandingan Sisi Kiri Sisi Kanan Terperinci EPM7128STC100-15N disebabkan oleh Intel dan EPM7128SQC100-10N disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.

Pengandingan Spesifikasi

Parametr EPM7128STC100-15N EPM7128SQC100-10N
Merek Intel Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Obsolete Aktif
Product Type CPLD (Complex Programmable Logic Device) —
Family MAX 7000S MAX 7000
Usable Gates 2,500 2,500
Macro Cells 128 128
Logic Array Blocks (LABs) 8 (16 macro cells each) 8 (16 macro cells each)
Maximum User I/O 84 —
Pin-to-Pin Logic Delay (tPD) 15 ns (-15 speed grade) —
Maximum Internal Frequency 76.9 MHz —
Supply Voltage (VCC) 5 V (4.75 V to 5.25 V) —
Supply Voltage (VCCIO) 3.3 V or 5 V (per bank) —
Technology CMOS EEPROM, in-system programmable —
Kemasan 100-pin TQFP 100-pin PQFP (BQFP)
Suhu Operasi 0C to +70C (commercial) -40C to +85C (industrial)
JTAG (IEEE 1149.1) Yes - in-system programming —
Output Options Totem-pole or open-drain (per pin) —
Dedicated Inputs 4 global inputs —
Status RoHS Non-RoHS (legacy SnPb finish typical) —
Status Lingkungan Hidup Obsolete (PDN effective 2017-06-01) —
Device Type — CPLD (Complex Programmable Logic Device)
User I/O Pins — 84
Propagation Delay (tPD) — 10 ns
Maximum Frequency — 100 MHz
Supply Voltage (VCCINT) — 5 V (4.75 V to 5.25 V)
I/O Voltage Tolerance — 3.3 V or 5 V (MultiVolt interface)
Configuration Memory — EEPROM (non-volatile)
Programming Interface — JTAG (IEEE Std 1149.1), 4-pin
Jenis Pemasangan — Surface Mount
Lead-Free / RoHS Status — Lead-free (N suffix)
Architecture Generation — Second-generation MAX

Laporan Datasheet & Sumber

Lihat Semua Produk Buat BOQ Minta Bao Harga