EPM7128STC100-15N vs EPM7128SQC100-10N Comparison

Detailed side-by-side comparison of EPM7128STC100-15N by Intel and EPM7128SQC100-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM7128STC100-15N EPM7128SQC100-10N
Brand Intel Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Active
Stock Status In Stock In Stock
Unit Price (USD) $9.20 $14.95
Product Type CPLD (Complex Programmable Logic Device) β€”
Family MAX 7000S MAX 7000
Usable Gates 2,500 2,500
Macro Cells 128 128
Logic Array Blocks (LABs) 8 (16 macro cells each) 8 (16 macro cells each)
Maximum User I/O 84 β€”
Pin-to-Pin Logic Delay (tPD) 15 ns (-15 speed grade) β€”
Maximum Internal Frequency 76.9 MHz β€”
Supply Voltage (VCC) 5 V (4.75 V to 5.25 V) β€”
Supply Voltage (VCCIO) 3.3 V or 5 V (per bank) β€”
Technology CMOS EEPROM, in-system programmable β€”
Package 100-pin TQFP 100-pin PQFP (BQFP)
Operating Temperature 0C to +70C (commercial) -40C to +85C (industrial)
JTAG (IEEE 1149.1) Yes - in-system programming β€”
Output Options Totem-pole or open-drain (per pin) β€”
Dedicated Inputs 4 global inputs β€”
RoHS Status Non-RoHS (legacy SnPb finish typical) β€”
Lifecycle Status Obsolete (PDN effective 2017-06-01) β€”
Device Type β€” CPLD (Complex Programmable Logic Device)
User I/O Pins β€” 84
Propagation Delay (tPD) β€” 10 ns
Maximum Frequency β€” 100 MHz
Supply Voltage (VCCINT) β€” 5 V (4.75 V to 5.25 V)
I/O Voltage Tolerance β€” 3.3 V or 5 V (MultiVolt interface)
Configuration Memory β€” EEPROM (non-volatile)
Programming Interface β€” JTAG (IEEE Std 1149.1), 4-pin
Mounting Type β€” Surface Mount
Lead-Free / RoHS Status β€” Lead-free (N suffix)
Architecture Generation β€” Second-generation MAX

Datasheets & Resources

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