EPM7160EQC100-20 vs EPM7160STC100-6N Pengandingan

Pengandingan Sisi Kiri Sisi Kanan Terperinci EPM7160EQC100-20 disebabkan oleh Altera dan EPM7160STC100-6N disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.

Altera
EPM7160EQC100-20 EPM7160EQC100-20 - MAX 7000 CPLD, 160 Macrocells, 100-Pin PQFP

EPM7160EQC100-20 - MAX 7000 CPLD, 160 Macrocells, 100-Pin PQFP

EPM7160EQC100-20 ⚠ Bahagian terakhir untuk beli

Pengandingan Spesifikasi

Parametr EPM7160EQC100-20 EPM7160STC100-6N
Merek Altera Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Masa Terakhir Dibeli Obsolete
Series MAX 7000 —
Family MAX 7000 CPLD MAX 7000S
Architecture CMOS EEPROM-based, non-volatile —
Usable Gates 3,200 —
Macrocells 160 —
Logic Array Blocks (LABs) 10 —
Maximum User I/Os 84 —
Pin-to-Pin Propagation Delay (tPD) 20 ns —
Maximum Internal Frequency (fCNT) 62.5 MHz —
Supply Voltage (VCCINT) 5 V nominal (4.75 V to 5.25 V) —
I/O Voltage Support 3.3 V or 5 V configurable —
Kemasan 100-pin Plastic Quad Flat Pack (PQFP, EQFP, EQC100) TQFP-100 (T100)
Jenis Pemasangan Surface Mount —
Suhu Operasi 0 °C to +90 °C (commercial) 0 °C to +70 °C (Commercial)
In-System Programmability Yes (IEEE 1149.1 JTAG, 4-pin) Yes (IEEE 1149.1 JTAG)
Reprogram Cycles (typical) 100 —
Status RoHS Not RoHS compliant (legacy Altera MAX 7000) [DATA_NEEDED: RoHS compliance]
Logic Elements per Macrocell 36 product terms (expandable) —
Logic Type — CPLD (Complex Programmable Logic Device)
Macro Cells — 160
User I/Os — 84
Gates (typical) — 3,200
Propagation Delay (tPD) — 6 ns
Internal Frequency — 149.3 MHz (max)
Tegangan Pemberi Arus — 5 V
Program Memory Type — EEPROM (non-volatile)
Package Code — LFQFP, S Gull-Wing
Logic Family — CMOS
I/O Banks — [DATA_NEEDED: I/O bank count]
Lead-Free — [DATA_NEEDED: lead-free status]

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