EPM7160EQC100-20 vs EPM7160STC100-6N 比較
詳細並排比較 EPM7160EQC100-20 由 Altera 與 EPM7160STC100-6N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM7160EQC100-20 | EPM7160STC100-6N |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 最後購買 | Obsolete |
| Series | MAX 7000 | — |
| Family | MAX 7000 CPLD | MAX 7000S |
| Architecture | CMOS EEPROM-based, non-volatile | — |
| Usable Gates | 3,200 | — |
| Macrocells | 160 | — |
| Logic Array Blocks (LABs) | 10 | — |
| Maximum User I/Os | 84 | — |
| Pin-to-Pin Propagation Delay (tPD) | 20 ns | — |
| Maximum Internal Frequency (fCNT) | 62.5 MHz | — |
| Supply Voltage (VCCINT) | 5 V nominal (4.75 V to 5.25 V) | — |
| I/O Voltage Support | 3.3 V or 5 V configurable | — |
| 封裝 | 100-pin Plastic Quad Flat Pack (PQFP, EQFP, EQC100) | TQFP-100 (T100) |
| 安裝類型 | Surface Mount | — |
| 工作溫度 | 0 °C to +90 °C (commercial) | 0 °C to +70 °C (Commercial) |
| In-System Programmability | Yes (IEEE 1149.1 JTAG, 4-pin) | Yes (IEEE 1149.1 JTAG) |
| Reprogram Cycles (typical) | 100 | — |
| RoHS 狀態 | Not RoHS compliant (legacy Altera MAX 7000) | [DATA_NEEDED: RoHS compliance] |
| Logic Elements per Macrocell | 36 product terms (expandable) | — |
| Logic Type | — | CPLD (Complex Programmable Logic Device) |
| Macro Cells | — | 160 |
| User I/Os | — | 84 |
| Gates (typical) | — | 3,200 |
| Propagation Delay (tPD) | — | 6 ns |
| Internal Frequency | — | 149.3 MHz (max) |
| 供應電壓 | — | 5 V |
| Program Memory Type | — | EEPROM (non-volatile) |
| Package Code | — | LFQFP, S Gull-Wing |
| Logic Family | — | CMOS |
| I/O Banks | — | [DATA_NEEDED: I/O bank count] |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |