EPM7160SQC160-6 vs EPM7160SQC160-7 Pengandingan

Pengandingan Sisi Kiri Sisi Kanan Terperinci EPM7160SQC160-6 disebabkan oleh Altera dan EPM7160SQC160-7 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.

Pengandingan Spesifikasi

Parametr EPM7160SQC160-6 EPM7160SQC160-7
Merek Altera Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Obsolete Obsolete
Series MAX 7000S —
Product Type CPLD (Complex Programmable Logic Device) —
Programmable Type In System Programmable (ISP), EEPROM-based —
Number of Macrocells 160 —
Number of Logic Elements/Blocks 10 LABs (Logic Array Blocks) —
Number of Usable Gates 3,200 —
Number of I/O Pins 104 —
Propagation Delay (tpd) 6 ns (max, pin-to-pin) —
Maximum Internal Frequency 167 MHz —
Supply Voltage (VCCINT) 4.75 V to 5.25 V (nominal 5 V) 4.75 V to 5.25 V (5.0 V nominal)
Logic Family CMOS, TTL-compatible I/O —
Suhu Operasi 0 C to 70 C (commercial) 0 °C to 70 °C (commercial)
Program/Erase Endurance 100 cycles (EEPROM) —
JTAG / Boundary Scan IEEE Std 1149.1 compliant —
Kemasan 160-pin PQFP (Plastic Quad Flat Pack), 28x28 mm body 160-pin PQFP (BQFP, 28x28 mm)
Jenis Pemasangan Surface Mount Surface Mount
Dedicated Input Pins 4 (GCLK1, GCLRn, OE1, OE2/GCLK2) —
Family — MAX 7000S
Macrocells — 160
Logic Array Blocks (LABs) — 10
Usable System Gates — 3,200
Product Terms per Macrocell — 32
Maximum User I/Os — 104
Global Clocks — 2
Speed Grade — -7 (7.5 ns pin-to-pin)
Maximum Propagation Delay (tPD) — 7.5 ns
Program Memory Type — EEPROM (in-system programmable)
JTAG (IEEE 1149.1) — Yes (ISP via JTAG)
PCI Compliance — PCI Local Bus Specification Revision 2.2
Status RoHS — Not Compliant (per Arrow listing)
Part Status — Obsolete

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