EPM7160SQC160-6 vs EPM7160SQC160-7 비교

다음의 상세 나란히 비교: EPM7160SQC160-6 제조: Altera 및 EPM7160SQC160-7 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.

사양 비교

파라미터 EPM7160SQC160-6 EPM7160SQC160-7
브랜드 Altera Altera
카테고리 FPGA & CPLD FPGA & CPLD
수명 주기 상태 Obsolete Obsolete
재고 상태 In Stock In Stock
단가 (USD) $5.45 $9.75
Series MAX 7000S —
Product Type CPLD (Complex Programmable Logic Device) —
Programmable Type In System Programmable (ISP), EEPROM-based —
Number of Macrocells 160 —
Number of Logic Elements/Blocks 10 LABs (Logic Array Blocks) —
Number of Usable Gates 3,200 —
Number of I/O Pins 104 —
Propagation Delay (tpd) 6 ns (max, pin-to-pin) —
Maximum Internal Frequency 167 MHz —
Supply Voltage (VCCINT) 4.75 V to 5.25 V (nominal 5 V) 4.75 V to 5.25 V (5.0 V nominal)
Logic Family CMOS, TTL-compatible I/O —
동작 온도 0 C to 70 C (commercial) 0 °C to 70 °C (commercial)
Program/Erase Endurance 100 cycles (EEPROM) —
JTAG / Boundary Scan IEEE Std 1149.1 compliant —
패키지 160-pin PQFP (Plastic Quad Flat Pack), 28x28 mm body 160-pin PQFP (BQFP, 28x28 mm)
실장 유형 Surface Mount Surface Mount
Dedicated Input Pins 4 (GCLK1, GCLRn, OE1, OE2/GCLK2) —
Family — MAX 7000S
Macrocells — 160
Logic Array Blocks (LABs) — 10
Usable System Gates — 3,200
Product Terms per Macrocell — 32
Maximum User I/Os — 104
Global Clocks — 2
Speed Grade — -7 (7.5 ns pin-to-pin)
Maximum Propagation Delay (tPD) — 7.5 ns
Program Memory Type — EEPROM (in-system programmable)
JTAG (IEEE 1149.1) — Yes (ISP via JTAG)
PCI Compliance — PCI Local Bus Specification Revision 2.2
RoHS 상태 — Not Compliant (per Arrow listing)
Part Status — Obsolete

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