EPM9320ARC208-10 vs EPM9320BC356-15 Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EPM9320ARC208-10 disebabkan oleh Altera dan EPM9320BC356-15 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Altera
EPM9320ARC208-10 - MAX 9000 CPLD, 320 Macro, 10ns | Altera
EPM9320ARC208-10 ⚠ Bahagian terakhir untuk beli
Pengandingan Spesifikasi
| Parametr | EPM9320ARC208-10 | EPM9320BC356-15 |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Masa Terakhir Dibeli | NRND |
| Device Family | MAX 9000 | — |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 320 | 320 |
| Usable Gates | 6,000 | — |
| Pin-to-Pin Delay (tPD) | 10 ns | — |
| Maximum Frequency | 144.9 MHz | — |
| Tegangan Pemberi Arus | 5.0 V | — |
| Logic Blocks (LABs) | 16 | — |
| Programmability | EEPROM, in-system programmable via JTAG | — |
| JTAG Support | IEEE Std. 1149.1 compliant | — |
| Speed/Power Optimization | Per-macrocell programmable, 50% power mode available | — |
| Kemasan | RQFP-208 (Power Quad Flat Pack) | 356-ball LBGA (BGA-356, 35x35 mm) |
| Jenis Pemasangan | Surface Mount | Surface Mount |
| Suhu Operasi | [DATA_NEEDED: operating temperature range] | — |
| Status RoHS | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS compliance status] |
| Family | — | MAX 9000 |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Architecture | — | Multiple Array MatriX (MAX) - third generation |
| Pin-to-Pin Delay (max) | — | 15 ns |
| Process Technology | — | CMOS EEPROM |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V (5.0 V typical) |
| In-System Programmability | — | Yes (5.0-V ISP via JTAG) |
| JTAG Interface | — | IEEE Std. 1149.1 compliant |
| Programmable Type | — | In System Programmable |
| Operating Temperature Grade | — | Commercial |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |