EPM9560RC-15 vs EPM9560GC280-15 Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EPM9560RC-15 disebabkan oleh Altera dan EPM9560GC280-15 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Altera
EPM9560RC-15 - 560-Macrocell MAX 9000 CPLD, 15ns, 240-RQFP | Altera / Intel
EPM9560RC-15 ⚠ Bahagian terakhir untuk beliAltera
EPM9560GC280-15 - MAX 9000 CPLD, 560 Macro Cells, 15ns CPGA280 | Intel / Altera
EPM9560GC280-15 ObsoletePengandingan Spesifikasi
| Parametr | EPM9560RC-15 | EPM9560GC280-15 |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Masa Terakhir Dibeli | Obsolete |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | EE PLD (CMOS EEPROM-based CPLD) |
| Macrocells | 560 | — |
| Usable Gates | 12,000 | — |
| Logic Array Blocks (LABs) | 16 (40 macrocells each) | — |
| Maximum User I/O Pins | 191 | — |
| Pin-to-Pin Delay (tPD1) | 15 ns | — |
| Supply Voltage (VCCINT) | 4.75 V to 5.25 V (5.0 V nominal) | — |
| Suhu Operasi | 0 C to +70 C (commercial) | — |
| Kemasan | 240-pin RQFP (32x32 mm) | — |
| Jenis Pemasangan | Surface Mount | Through-Hole |
| Programming Interface | IEEE Std. 1149.1 JTAG (ISP) | — |
| Process Technology | CMOS EEPROM | — |
| Architecture | Multiple Array MatriX (MAX) - third generation | Multiple Array MatriX (MAX) |
| Status RoHS | [DATA_NEEDED: RoHS status] | Non-compliant (ceramic CPGA, contains lead) |
| In-System Programmability | Yes (5.0 V ISP via JTAG) | — |
| Macro Cells | — | 560 |
| Typical Gates | — | 12,000 |
| Maximum Operating Frequency | — | 117.6 MHz |
| Propagation Delay (tpd) | — | 15 ns (speed grade -15) |
| Propagation Delay (alternate datasheet figure) | — | 16.6 ns |
| Supply Voltage (VCCINT/VCCIO) | — | 5.0 V |
| Operating Temperature (Commercial) | — | 0C to +70C |
| Package Type | — | CPGA-280 (Ceramic Pin Grid Array, 280 pins) |
| Programmability | — | In-System Programmable (ISP) via JTAG IEEE 1149.1 |
| Technology | — | CMOS EEPROM, 0.5 um process (MAX third-gen) |
| Status Lingkungan Hidup | — | Obsolete (legacy Altera MAX 9000 family) |