EPM9560RC208-18 vs EPM9560RC208-17 Pengandingan

Pengandingan Sisi Kiri Sisi Kanan Terperinci EPM9560RC208-18 disebabkan oleh Altera dan EPM9560RC208-17 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.

Altera
EPM9560RC208-18 EPM9560RC208-18 - MAX 9000 CPLD 560 Macro Cells 5V | Altera

EPM9560RC208-18 - MAX 9000 CPLD 560 Macro Cells 5V | Altera

EPM9560RC208-18 ✗ Akhir Hayat

Pengandingan Spesifikasi

Parametr EPM9560RC208-18 EPM9560RC208-17
Merek Altera Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Akhir Hidup NRND
Device Family MAX 9000 (EPM9560) —
Logic Type EEPROM-based Complex Programmable Logic Device (CPLD) —
Usable Gates 12,000 gates 12,000
Macrocells 560 macrocells —
Propagation Delay (tPD) 18 ns (speed grade -18) —
Maximum Operating Frequency 117.6 MHz (family -15 grade reference) —
Tegangan Pemberi Arus 5 V —
I/O Voltage Compatibility 3.3 V or 5 V —
User I/O Lines 149 I/O lines —
Flip-Flops 772 flip-flops —
Kemasan 208-pin RQFP (Power Quad Flat Pack) 208-pin RQFP (RC208)
Package JESD-30 Code S-PQFP-G208 —
Jenis Pemasangan Surface Mount Surface Mount
Configuration Memory EEPROM (non-volatile, no external config PROM) —
Technology CMOS —
Suhu Operasi [DATA_NEEDED: operating temperature range] —
Status RoHS [DATA_NEEDED: RoHS status] —
Status Lingkungan Hidup EOL / mature (per Altera product discontinuance notice) —
Family — MAX 9000
Product Type — CPLD (EPLD, in-system programmable)
Macro Cells — 560
Logic Array Blocks (LABs) — 16
Pin-to-Pin Delay (tPD) — 17 ns
Maximum Counter Frequency — 117.6 MHz
User I/O Pins — 212
Supply Voltage (VCC) — 5 V
Programming Technology — EEPROM (in-system programmable)
Program/Erase Cycles — 100 minimum
JTAG (IEEE 1149.1) Support — Yes
Architecture — Third-generation MAX (AND-OR PLA)

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