EPM9560RI205-15 vs EPM9560RI208-15N Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EPM9560RI205-15 disebabkan oleh Altera dan EPM9560RI208-15N disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Pengandingan Spesifikasi
| Parametr | EPM9560RI205-15 | EPM9560RI208-15N |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | Obsolete |
| Family | MAX 9000 | — |
| Device | EPM9560 | — |
| Logic Capacity | 6,000 usable gates | — |
| Macrocells | 212 | — |
| Logic Array Blocks (LABs) | 20 | — |
| Maximum User I/O Pins | 164 | — |
| Speed Grade | -15 (15 ns pin-to-pin delay) | -15 |
| Propagation Delay (tpd) | 15 ns | — |
| Kemasan | RQFP-205 (PowerQuad4) | 208-pin RQFP (Ruggedized Quad Flat Pack) |
| Supply Voltage (VCC) | 5.0 V | — |
| Technology | CMOS EEPROM | — |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) | — |
| Suhu Operasi | -40 C to +85 C (industrial) | 0C to 70C (Commercial) |
| Jenis Pemasangan | Surface Mount | — |
| Status RoHS | [DATA_NEEDED: rohs_compliance] | [DATA_NEEDED: RoHS status] |
| Manufacturer | — | Altera (Intel Programmable Solutions Group) |
| Device Family | — | MAX 9000 |
| Device Type | — | EPLD (Erasable Programmable Logic Device) |
| Architecture | — | Multiple Array MatriX (MAX), 3rd generation |
| Configuration Memory | — | CMOS EEPROM, in-system programmable |
| Total Pins | — | 356 (per third-party catalog; see _validation_note) |
| Package Pin Count | — | 208 |
| Terminal Form | — | Gull Wing |
| Package Code | — | HFQFP |
| User I/Os | — | 216 (per DigiChip specification; see _validation_note) |
| Maximum Internal Frequency | — | 145 MHz |
| Propagation Delay (tPD) | — | 11.4 ns (15 ns speed grade) |
| Tegangan Pemberi Arus | — | 5.0 V |
| Temperature Grade | — | Industrial (per Vyrian/Partstack listings) |
| Logic Family | — | CMOS |
| Programming Interface | — | IEEE 1149.1 JTAG, 5.0-V in-system |