RTAX250SL-CG624E vs RTAX250S-CG624B Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci RTAX250SL-CG624E disebabkan oleh Microchip Technology dan RTAX250S-CG624B disebabkan oleh Microchip Technology. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Microchip Technology
RTAX250SL-CG624E - 250K-Gate Rad-Tolerant FPGA | Microchip
RTAX250SL-CG624E ✓ AktifMicrochip Technology
RTAX250S-CG624B - 250K Gate Rad-Tolerant FPGA CCGA-624 | Microchip
RTAX250S-CG624B ✓ AktifPengandingan Spesifikasi
| Parametr | RTAX250SL-CG624E | RTAX250S-CG624B |
|---|---|---|
| Merek | Microchip Technology | Microchip Technology |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Aktif | Aktif |
| Family | RTAX-S/SL Radiation-Tolerant FPGA | — |
| System Gates | 250000 | 250000 gates |
| Logic Cells (CLBs) | 2816 | 2816 cells |
| Maximum Frequency | 649 MHz | — |
| Process Technology | 0.15 um CMOS | 0.15 um CMOS |
| Core Supply Voltage | 1.5 V | 1.5 V |
| Supply Voltage Tolerance | +/-0.15 V | — |
| Maximum Combinatorial Delay | 0.93 ns | — |
| Kemasan | 624-Pin CCGA (Ceramic Column Grid Array) | — |
| Suhu Operasi | -55C to +125C | -55C to +125C |
| Logic Family | CMOS | CMOS |
| Radiation Tolerance | SEU-hardened registers; SEU rate < 10-10 errors/bit-day | SEU rate < 10^-10 errors/bit-day; SEU-hardened registers |
| Embedded Memory | Embedded SRAM with built-in FIFO control logic | Embedded SRAM with built-in FIFO control logic |
| Clocking | Segmentable clocks, chip-wide highway routing | — |
| Jenis Pemasangan | Surface Mount | Surface Mount |
| Status RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Programmability | Live at power-up, true single-chip | — |
| Maximum System Frequency | — | 649 MHz |
| Package Type | — | CCGA-624 (Ceramic Column Grid Array, 624 pins) |
| Configuration | — | One-time programmable antifuse, live at power-up |
| Product Family | — | RTAX-S / RTAX-SL Radiation-Tolerant FPGA |
| Architecture Basis | — | Microsemi Axcelerator commercial family |
| TMR Requirement | — | Eliminated for registers via SEU hardening |
| Speed Grade Option | — | Standard; -1 grade approximately 15% faster |
| I/O Supply Voltage | — | [DATA_NEEDED: I/O bank voltage] |