RTAX250SL-CG624V vs RTAX250SL-1CG624E Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci RTAX250SL-CG624V disebabkan oleh Microchip Technology dan RTAX250SL-1CG624E disebabkan oleh Microchip Technology. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Microchip Technology
RTAX250SL-CG624V - 250k-Gate Rad-Tolerant FPGA | Microchip
RTAX250SL-CG624V ✓ AktifMicrochip Technology
RTAX250SL-1CG624E - 250K Gate Rad-Tolerant FPGA, CCGA-624 | Microchip
RTAX250SL-1CG624E ✓ AktifPengandingan Spesifikasi
| Parametr | RTAX250SL-CG624V | RTAX250SL-1CG624E |
|---|---|---|
| Merek | Microchip Technology | Microchip Technology |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Aktif | Aktif |
| Equivalent System Gates | 250000 | 250,000 gates |
| Logic Cells | 4224 | 4224 |
| CLB Count | 2816 | — |
| User I/O (Inputs) | 248 | — |
| User I/O (Outputs) | 248 | — |
| Core Supply Voltage | 1.425 V to 1.575 V | 1.5 V (1.425 V to 1.575 V) |
| Process Technology | CMOS | 0.15 um CMOS |
| Program Technology | Antifuse (one-time programmable) | — |
| Kemasan | 624-pin Ceramic Column Grid Array (CG624) | 624-ball Ceramic Column Grid Array (CCGA-624) |
| Embedded SRAM | Yes (with built-in FIFO control logic) | — |
| Configuration Device Required | No (live at power-up) | — |
| Radiation Tolerance | Radiation-tolerant (space flight qualified family) | SEU-immune to specified LET threshold; SEU rate < 10-10 errors/bit-day |
| Family | RTAX-S/SL and RTAX-DSP RadTolerant FPGAs | — |
| Suhu Operasi | [DATA_NEEDED: operating temperature range] | -55C to +125C |
| Speed Grade | Standard (C) commercial flight grade; -1 speed variant available | — |
| Jenis Pemasangan | Surface Mount | Surface Mount (ceramic column grid array) |
| Status RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Configurable Logic Blocks (CLBs) | — | 2816 |
| User I/O | — | 248 inputs / 248 outputs |
| Maximum Combinatorial Delay (CLB) | — | 0.93 ns |
| Maximum System Frequency | — | 649 MHz |
| Logic Family | — | CMOS |
| SEU Mitigation | — | SEU-hardened registers (no external TMR required) |
| Embedded Memory | — | Embedded SRAM with built-in FIFO control logic |
| Configuration | — | Live-at-power-up, true single-chip operation |
| I/O Supply Voltage | — | [DATA_NEEDED: I/O bank voltage] |