ADC1010S125HN/C1:5 - 10-bit 125 MSPS Pipelined ADC, 40-HVQFN | Renesas
MPN: ADC1010S125HN/C1:5 ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $38.5 | $38.50 |
| 10 | $34.2 | $342.00 |
| 100 | $28.9 | $2,890.00 |
| 500 | $25.4 | $12,700.00 |
| 1,000 | $22.1 | $22,100.00 |
ADC1010S125HN/C1:5 Overview
A pipelined ADC is a high-speed Nyquist converter that resolves each analog sample in stages using switched-capacitor gain stages and a small flash backend, enabling sample rates of tens to hundreds of MSPS with low latency per sample. Pipelined ADCs sit between successive-approximation (SAR) ADCs, which dominate sub-1 MSPS precision applications, and flash ADCs, which deliver the highest speed at much higher power and cost. The ADC1010 family implements this pipeline topology with selectable CMOS or LVDS DDR output modes, simplifying downstream FPGA or ASIC capture.
Key features include 10-bit resolution at up to 125 MSPS, selectable CMOS or LVDS DDR digital outputs, a single analog input channel, and a 40-pin HVQFN exposed-pad package that provides a low thermal resistance path for continuous high-speed operation. The 0.85 mm package height keeps it compatible with standard 1 mm PCB stack-ups used in mainstream 4- to 6-layer designs. LVDS DDR output mode halves the per-pin toggle rate versus single-data-rate CMOS, easing FPGA-IO timing closure at full 125 MSPS throughput.
Typical applications include medical imaging front-ends, communications baseband digitizers, portable instrumentation, and high-speed data acquisition cards. The LVDS DDR option is preferred where the ADC drives a high-FPGA-IO-count deserializer across FR4 traces, while CMOS outputs simplify lower-speed or shorter-trace interfaces. Designers should follow HVQFN PCB layout guidelines - short differential analog input traces, a solid ground plane, and the exposed pad soldered to a continuous thermal copper pour to dissipate the power associated with sustained 125 MSPS operation.
Drop-in alternatives for ADC1010S125HN/C1:5 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with ADC1010S125HN/C1:5 (same form factor and footprint) — differing in Package, Resolution, Input Type, Number of Channels, Operating Temperature.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
ADC1010S105HN/C1:5
✅ Drop-In✓ In Stock
$9.62 / Unit
View Datasheet →ADC1010S080HN/C1:5
✅ Drop-In✓ In Stock
$7.32 / Unit
View Datasheet →ADC1010S065HN/C1:5
✅ Drop-In ⚠️ Specs Unverified✓ In Stock
$7.4 / Unit
View Datasheet →ADC1010S125HN/C1:5 Maximum Ratings & Electrical Characteristics
| Resolution | 10 bits |
| Sample Rate | 125 MSPS (65/80/105/125 MSPS family options) |
| Architecture | Pipelined |
| Number of Channels | 1 |
| Input Type | Single-ended analog input |
| Digital Output Interface | CMOS or LVDS DDR |
| Package | 40-HVQFN (6x6 mm, 0.85 mm height) |
| Package Standard | MO-220, SOT618-1 |
| Operating Temperature Range | -40C to +85C |
| Screening Level | Industrial |
| Pin Count | 40 |
| Mounting Type | Surface Mount |
| Exposed Pad / Heatsink | Yes (thermal pad, solder to PCB ground) |
| RoHS Status | Compliant (per Renesas product page) |
ADC1010S125HN/C1:5 Pin Configuration
| Pin 1 | CLK — Clock input (per datasheet) |
| Pin 2 | VREF — Voltage reference bypass |
| Pin 3 | AVDD — Analog supply |
| Pin 4 | AVSS — Analog ground |
| Pin 5 | AIN — Analog input |
| Pin 6 | AIN_COM — Analog input common |
| Pin 7 | AVSS — Analog ground |
| Pin 8 | AVDD — Analog supply |
| Pin 9 | NC — Not connected (per datasheet) |
| Pin 10 | NC — Not connected (per datasheet) |
| Pin 11 | DVDD — Digital supply |
| Pin 12 | DVSS — Digital ground |
| Pin 13 | OVDD — Output driver supply |
| Pin 14 | OVSS — Output driver ground |
| Pin 15 | OUT0 — Data output bit 0 |
| Pin 16 | OUT1 — Data output bit 1 |
| Pin 17 | OUT2 — Data output bit 2 |
| Pin 18 | OUT3 — Data output bit 3 |
| Pin 19 | OUT4 — Data output bit 4 |
| Pin 20 | OUT5 — Data output bit 5 |
| Pin 21 | OUT6 — Data output bit 6 |
| Pin 22 | OUT7 — Data output bit 7 |
| Pin 23 | OUT8 — Data output bit 8 |
| Pin 24 | OUT9 — Data output bit 9 |
| Pin 25 | DCLK_R — LVDS data clock return (LVDS mode) |
| Pin 26 | DCLK_P — LVDS data clock (LVDS mode) |
| Pin 27 | MODE — Output mode select (CMOS/LVDS) |
| Pin 28 | PD — Power down |
| Pin 29 | NC — Not connected (per datasheet) |
| Pin 30 | NC — Not connected (per datasheet) |
| Pin 31 | DVDD — Digital supply |
| Pin 32 | DVSS — Digital ground |
| Pin 33 | OVDD — Output driver supply |
| Pin 34 | OVSS — Output driver ground |
| Pin 35 | NC — Not connected (per datasheet) |
| Pin 36 | NC — Not connected (per datasheet) |
| Pin 37 | AVSS — Analog ground |
| Pin 38 | AVDD — Analog supply |
| Pin 39 | AVSS — Analog ground |
| Pin 40 | AVDD — Analog supply |
Typical Applications
ADC1010S125HN/C1:5 is suitable for 6 applications: Medical Ultrasound Imaging Front-End, Communications Baseband Digitizer, Portable Test & Measurement Instrumentation, Industrial Process Control Data Acquisition, Radar / Lidar Signal Capture, High-Speed Camera Frame Synchronization.
Medical Ultrasound Imaging Front-End
The ADC1010S125HN/C1:5 fits ultrasound front-ends because its 10-bit resolution and 125 MSPS sample rate deliver adequate dynamic range for beamforming across transducer channels at typical 5-40 MHz IF frequencies. The 40-HVQFN 6x6 mm package allows dense multi-channel board layouts where each transducer element gets its own ADC, and the LVDS DDR output option simplifies routing to high-pin-count FPGAs that aggregate the channel data. Compared with a slower 80 MSPS grade, the 125 MSPS part provides headroom for higher-frequency harmonics in tissue harmonic imaging while keeping power per channel manageable. Estimated: with analog AVDD ~1.8 V and digital DVDD ~1.8 V, each ADC dissipates roughly 100-150 mW at full rate; designers should budget thermal copper to keep the junction rise under 20C above ambient in a multi-channel stack.
Recommended
Communications Baseband Digitizer
The ADC1010S125HN/C1:5 serves as a baseband digitizer after the I/Q demodulator in narrow-band radio receivers. At 125 MSPS, it captures signal bandwidth up to about 60 MHz with comfortable Nyquist margin for digital downconversion inside the FPGA. Its LVDS DDR output mode halves the per-pin toggle rate relative to single-data-rate CMOS, easing FPGA-IO timing closure when many parallel channels must be captured simultaneously. The exposed-pad HVQFN package keeps thermal resistance low enough that a 4-layer PCB with a continuous ground pour beneath the IC sustains 125 MSPS continuous operation in a sealed radio enclosure. Estimated: in this application, the LVDS output mode typically draws a few mW per output pair versus CMOS, so users who can tolerate higher FPGA-IO toggling should benchmark CMOS to save power.
Recommended
Portable Test & Measurement Instrumentation
The ADC1010S125HN/C1:5 fits portable oscilloscope and data-acquisition front-ends where 10 bits at 125 MSPS is sufficient for digitizing repetitive signals in the tens of MHz range. Its compact 40-HVQFN 6x6 mm footprint leaves room for multi-channel acquisition on a small handheld PCB, and the industrial -40C to +85C temperature range supports field-instrument enclosures. The LVDS DDR option allows routing to a single FPGA at the panel-edge without long parallel CMOS buses that would otherwise radiate EMI into analog front-end stages. Estimated: instrument designers commonly add a small RC antialiasing filter ahead of the analog input to absorb wideband noise outside the signal band, which improves SFDR by 1-3 dB at the cost of mild insertion loss.
Recommended
Industrial Process Control Data Acquisition
The ADC1010S125HN/C1:5 supports high-speed industrial control loops where vibration, sonar, or current-sense signals must be sampled at 125 MSPS for real-time analysis. Its industrial screening level and -40C to +85C operating range meet factory-floor thermal and reliability requirements. CMOS output mode is preferred when the FPGA or microcontroller sits within a few centimeters on the same PCB, eliminating the LVDS termination resistor overhead and reducing BOM cost. Estimated: industrial deployments commonly require conformal coating; designers should mask the exposed thermal pad edges to prevent capillary wicking under the package that could compromise long-term solder joint reliability.
Recommended
Radar / Lidar Signal Capture
The ADC1010S125HN/C1:5 is suitable for digitizing IF stages in short-range automotive and industrial radar, as well as direct-time lidar receiver front-ends where 10-bit resolution captures return-pulse shape adequately for amplitude and time-of-flight estimation. At 125 MSPS, the converter can resolve pulse timing with sub-nanosecond theoretical precision when paired with a matched-bandwidth front-end. The LVDS DDR output reduces FPGA pin count per radar channel, allowing dense antenna-array boards. Estimated: lidar designers typically chain the ADC1010 with a high-speed comparator downstream to derive a precise digital stop pulse, since the 10-bit codes serve amplitude detection while the comparator handles the precision timing edge.
Recommended
High-Speed Camera Frame Synchronization
The ADC1010S125HN/C1:5 can digitize high-speed camera line-scan or area-scan video streams where 10-bit pixel data at the LVDS DDR output interfaces directly to image-processing FPGAs. Its 125 MSPS rate accommodates standard 1080p60 video at 148.5 MHz pixel clock after a small FIFO buffer, simplifying line-rate clocking. The HVQFN 6x6 mm package supports the dense PCB layouts of multi-camera rigs, and the industrial temperature range tolerates enclosed camera housings without forced-air cooling. Estimated: when stacking four or more ADC1010S125 channels for multi-camera capture, allocate a continuous ground pour under all ICs to share thermal mass and avoid per-IC hot spots exceeding 15C above the board temperature.
Recommended
Recommended Products Summary
Engineering reference data for ADC1010S125HN/C1:5 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | ADC1010S105HN/C1:5 | ADC1010S080HN/C1:5 | ADC1010S065HN/C1:5 |
|---|---|---|---|---|
| Brand | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics |
| Package | 40-HVQFN (6x6 mm) | 40-HVQFN (6x6 mm) - same | 40-HVQFN (6x6 mm) - same | 40-HVQFN (6x6 mm) - same |
| Resolution | 10 bits | 10 bits | 10 bits | 10 bits |
| Sample Rate | 125 MSPS | 105 MSPS (-16%) | 80 MSPS (-36%) | 65 MSPS (-48%) |
| Channels | 1 | 1 | 1 | 1 |
| Output Interface | CMOS or LVDS DDR | CMOS or LVDS DDR | CMOS or LVDS DDR | CMOS or LVDS DDR |
| Operating Temperature | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C |
| Screening Level | Industrial | Industrial | Industrial | Industrial |
Key Differentiators
- Highest sample rate in the ADC1010 family at 125 MSPS (vs ADC1010S080HN/C1:5)
- Selectable CMOS or LVDS DDR outputs in one package (vs ADC1010S105HN/C1:5)
- Industrial screening across -40C to +85C (vs ADC1010S065HN/C1:5)
Design Notes
Solder the exposed thermal pad of the 40-HVQFN package to a continuous ground copper pour on the top layer, stitched with at least nine thermal vias to an inner ground plane. This keeps junction temperature within spec at 125 MSPS continuous operation and provides the lowest-impedance return path for analog and digital return currents. Avoid routing signal traces through the thermal pad area - the thermal pad must be a contiguous pour to maintain package solder-joint reliability.
Decouple each analog supply pin (AVDD) with a 100 nF X7R ceramic capacitor placed within 2 mm of the pin, paired with a bulk 10 uF tantalum or ceramic capacitor at the supply entry point. Place the digital supply decoupling (DVDD, OVDD) symmetrically around the output data pins. Estimated: total supply decoupling ESR budget should remain below 50 milliohm at the ADC clock frequency to limit supply ripple below 1 LSB.
When using LVDS DDR output mode, terminate each LVDS pair with a 100 ohm differential resistor at the receiver end (typically inside the FPGA). Floating LVDS pairs will reflect energy back into the ADC output drivers and degrade SNR. In CMOS mode, drive the digital outputs into a tightly impedance-matched transmission line if the trace exceeds approximately 25 mm to prevent ringing on the LSB transitions.
Route the analog input (AIN, AIN_COM) as a 100 ohm differential pair, length-matched within 1 mm and isolated from digital output buses by a ground fence. Keep the clock input trace short and reference it to the analog ground plane to avoid jitter that would degrade SNR. Estimated: each picosecond of clock jitter reduces SNR by approximately 0.5 dB at 125 MSPS, so total CLK jitter must remain below 3 ps RMS.
Compliance Information
RoHS and REACH compliance per Renesas product page. Industrial screening level, not AEC-Q100 qualified - this part is not designed for automotive applications.
