ADC1010S125HN/C1:5 - 10-bit 125 MSPS Pipelined ADC, 40-HVQFN | Renesas
부품 번호: ADC1010S125HN/C1:5 ✓ 활성| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $38.5 | $38.50 |
| 10 | $34.2 | $342.00 |
| 100 | $28.9 | $2,890.00 |
| 500 | $25.4 | $12,700.00 |
| 1,000 | $22.1 | $22,100.00 |
ADC1010S125HN/C1:5 개요
A pipelined ADC is a high-speed Nyquist converter that resolves each analog sample in stages using switched-capacitor gain stages and a small flash backend, enabling sample rates of tens to hundreds of MSPS with low latency per sample. Pipelined ADCs sit between successive-approximation (SAR) ADCs, which dominate sub-1 MSPS precision applications, and flash ADCs, which deliver the highest speed at much higher power and cost. The ADC1010 family implements this pipeline topology with selectable CMOS or LVDS DDR output modes, simplifying downstream FPGA or ASIC capture.
Key features include 10-bit resolution at up to 125 MSPS, selectable CMOS or LVDS DDR digital outputs, a single analog input channel, and a 40-pin HVQFN exposed-pad package that provides a low thermal resistance path for continuous high-speed operation. The 0.85 mm package height keeps it compatible with standard 1 mm PCB stack-ups used in mainstream 4- to 6-layer designs. LVDS DDR output mode halves the per-pin toggle rate versus single-data-rate CMOS, easing FPGA-IO timing closure at full 125 MSPS throughput.
Typical applications include medical imaging front-ends, communications baseband digitizers, portable instrumentation, and high-speed data acquisition cards. The LVDS DDR option is preferred where the ADC drives a high-FPGA-IO-count deserializer across FR4 traces, while CMOS outputs simplify lower-speed or shorter-trace interfaces. Designers should follow HVQFN PCB layout guidelines - short differential analog input traces, a solid ground plane, and the exposed pad soldered to a continuous thermal copper pour to dissipate the power associated with sustained 125 MSPS operation.
드롭인 대체품: ADC1010S125HN/C1:5 — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
이 시리즈의 변형
다음과 드롭인 호환되는 동일 시리즈 모델: ADC1010S125HN/C1:5 (동일 폼 팩터 및 풋프린트) — 차이점: Package, Resolution, Input Type, Number of Channels, Operating Temperature.
빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:
ADC1010S105HN/C1:5
✅ 드롭인✓ 재고 있음
$9.62 / 개
데이터시트 보기 →ADC1010S080HN/C1:5
✅ 드롭인✓ 재고 있음
$7.32 / 개
데이터시트 보기 →ADC1010S065HN/C1:5
✅ 드롭인 ⚠️ 사양 미검증✓ 재고 있음
$7.4 / 개
데이터시트 보기 →ADC1010S125HN/C1:5 최대 정격 & 전기적 특성
| 분해능 | 10 bits |
| Sample Rate | 125 MSPS (65/80/105/125 MSPS family options) |
| Architecture | Pipelined |
| Number of Channels | 1 |
| Input Type | Single-ended analog input |
| Digital Output Interface | CMOS or LVDS DDR |
| 패키지 | 40-HVQFN (6x6 mm, 0.85 mm height) |
| Package Standard | MO-220, SOT618-1 |
| 동작 온도 범위 | -40C to +85C |
| Screening Level | Industrial |
| 핀 수 | 40 |
| 실장 유형 | Surface Mount |
| Exposed Pad / Heatsink | Yes (thermal pad, solder to PCB ground) |
| RoHS 상태 | Compliant (per Renesas product page) |
ADC1010S125HN/C1:5 핀 구성
| 핀 1 | CLK — Clock input (per datasheet) |
| 핀 2 | VREF — Voltage reference bypass |
| 핀 3 | AVDD — Analog supply |
| 핀 4 | AVSS — Analog ground |
| 핀 5 | AIN — Analog input |
| 핀 6 | AIN_COM — Analog input common |
| 핀 7 | AVSS — Analog ground |
| 핀 8 | AVDD — Analog supply |
| 핀 9 | NC — Not connected (per datasheet) |
| 핀 10 | NC — Not connected (per datasheet) |
| 핀 11 | DVDD — Digital supply |
| 핀 12 | DVSS — Digital ground |
| 핀 13 | OVDD — Output driver supply |
| 핀 14 | OVSS — Output driver ground |
| 핀 15 | OUT0 — Data output bit 0 |
| 핀 16 | OUT1 — Data output bit 1 |
| 핀 17 | OUT2 — Data output bit 2 |
| 핀 18 | OUT3 — Data output bit 3 |
| 핀 19 | OUT4 — Data output bit 4 |
| 핀 20 | OUT5 — Data output bit 5 |
| 핀 21 | OUT6 — Data output bit 6 |
| 핀 22 | OUT7 — Data output bit 7 |
| 핀 23 | OUT8 — Data output bit 8 |
| 핀 24 | OUT9 — Data output bit 9 |
| 핀 25 | DCLK_R — LVDS data clock return (LVDS mode) |
| 핀 26 | DCLK_P — LVDS data clock (LVDS mode) |
| 핀 27 | MODE — Output mode select (CMOS/LVDS) |
| 핀 28 | PD — Power down |
| 핀 29 | NC — Not connected (per datasheet) |
| 핀 30 | NC — Not connected (per datasheet) |
| 핀 31 | DVDD — Digital supply |
| 핀 32 | DVSS — Digital ground |
| 핀 33 | OVDD — Output driver supply |
| 핀 34 | OVSS — Output driver ground |
| 핀 35 | NC — Not connected (per datasheet) |
| 핀 36 | NC — Not connected (per datasheet) |
| 핀 37 | AVSS — Analog ground |
| 핀 38 | AVDD — Analog supply |
| 핀 39 | AVSS — Analog ground |
| 핀 40 | AVDD — Analog supply |
일반적인 애플리케이션
ADC1010S125HN/C1:5 적합 용도: 6 애플리케이션s: Medical Ultrasound Imaging Front-End, Communications Baseband Digitizer, Portable Test & Measurement Instrumentation, Industrial Process Control Data Acquisition, Radar / Lidar Signal Capture, High-Speed Camera Frame Synchronization.
Medical Ultrasound Imaging Front-End
The ADC1010S125HN/C1:5 fits ultrasound front-ends because its 10-bit resolution and 125 MSPS sample rate deliver adequate dynamic range for beamforming across transducer channels at typical 5-40 MHz IF frequencies. The 40-HVQFN 6x6 mm package allows dense multi-channel board layouts where each transducer element gets its own ADC, and the LVDS DDR output option simplifies routing to high-pin-count FPGAs that aggregate the channel data. Compared with a slower 80 MSPS grade, the 125 MSPS part provides headroom for higher-frequency harmonics in tissue harmonic imaging while keeping power per channel manageable. Estimated: with analog AVDD ~1.8 V and digital DVDD ~1.8 V, each ADC dissipates roughly 100-150 mW at full rate; designers should budget thermal copper to keep the junction rise under 20C above ambient in a multi-channel stack.
추천
Communications Baseband Digitizer
The ADC1010S125HN/C1:5 serves as a baseband digitizer after the I/Q demodulator in narrow-band radio receivers. At 125 MSPS, it captures signal bandwidth up to about 60 MHz with comfortable Nyquist margin for digital downconversion inside the FPGA. Its LVDS DDR output mode halves the per-pin toggle rate relative to single-data-rate CMOS, easing FPGA-IO timing closure when many parallel channels must be captured simultaneously. The exposed-pad HVQFN package keeps thermal resistance low enough that a 4-layer PCB with a continuous ground pour beneath the IC sustains 125 MSPS continuous operation in a sealed radio enclosure. Estimated: in this application, the LVDS output mode typically draws a few mW per output pair versus CMOS, so users who can tolerate higher FPGA-IO toggling should benchmark CMOS to save power.
추천
Portable Test & Measurement Instrumentation
The ADC1010S125HN/C1:5 fits portable oscilloscope and data-acquisition front-ends where 10 bits at 125 MSPS is sufficient for digitizing repetitive signals in the tens of MHz range. Its compact 40-HVQFN 6x6 mm footprint leaves room for multi-channel acquisition on a small handheld PCB, and the industrial -40C to +85C temperature range supports field-instrument enclosures. The LVDS DDR option allows routing to a single FPGA at the panel-edge without long parallel CMOS buses that would otherwise radiate EMI into analog front-end stages. Estimated: instrument designers commonly add a small RC antialiasing filter ahead of the analog input to absorb wideband noise outside the signal band, which improves SFDR by 1-3 dB at the cost of mild insertion loss.
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Industrial Process Control Data Acquisition
The ADC1010S125HN/C1:5 supports high-speed industrial control loops where vibration, sonar, or current-sense signals must be sampled at 125 MSPS for real-time analysis. Its industrial screening level and -40C to +85C operating range meet factory-floor thermal and reliability requirements. CMOS output mode is preferred when the FPGA or microcontroller sits within a few centimeters on the same PCB, eliminating the LVDS termination resistor overhead and reducing BOM cost. Estimated: industrial deployments commonly require conformal coating; designers should mask the exposed thermal pad edges to prevent capillary wicking under the package that could compromise long-term solder joint reliability.
추천
Radar / Lidar Signal Capture
The ADC1010S125HN/C1:5 is suitable for digitizing IF stages in short-range automotive and industrial radar, as well as direct-time lidar receiver front-ends where 10-bit resolution captures return-pulse shape adequately for amplitude and time-of-flight estimation. At 125 MSPS, the converter can resolve pulse timing with sub-nanosecond theoretical precision when paired with a matched-bandwidth front-end. The LVDS DDR output reduces FPGA pin count per radar channel, allowing dense antenna-array boards. Estimated: lidar designers typically chain the ADC1010 with a high-speed comparator downstream to derive a precise digital stop pulse, since the 10-bit codes serve amplitude detection while the comparator handles the precision timing edge.
추천
High-Speed Camera Frame Synchronization
The ADC1010S125HN/C1:5 can digitize high-speed camera line-scan or area-scan video streams where 10-bit pixel data at the LVDS DDR output interfaces directly to image-processing FPGAs. Its 125 MSPS rate accommodates standard 1080p60 video at 148.5 MHz pixel clock after a small FIFO buffer, simplifying line-rate clocking. The HVQFN 6x6 mm package supports the dense PCB layouts of multi-camera rigs, and the industrial temperature range tolerates enclosed camera housings without forced-air cooling. Estimated: when stacking four or more ADC1010S125 channels for multi-camera capture, allocate a continuous ground pour under all ICs to share thermal mass and avoid per-IC hot spots exceeding 15C above the board temperature.
추천
추천 제품 요약
엔지니어링 참조 데이터: ADC1010S125HN/C1:5 — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | ADC1010S105HN/C1:5 | ADC1010S080HN/C1:5 | ADC1010S065HN/C1:5 |
|---|---|---|---|---|
| Brand | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics |
| Package | 40-HVQFN (6x6 mm) | 40-HVQFN (6x6 mm) - same | 40-HVQFN (6x6 mm) - same | 40-HVQFN (6x6 mm) - same |
| Resolution | 10 bits | 10 bits | 10 bits | 10 bits |
| Sample Rate | 125 MSPS | 105 MSPS (-16%) | 80 MSPS (-36%) | 65 MSPS (-48%) |
| Channels | 1 | 1 | 1 | 1 |
| Output Interface | CMOS or LVDS DDR | CMOS or LVDS DDR | CMOS or LVDS DDR | CMOS or LVDS DDR |
| Operating Temperature | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C |
| Screening Level | Industrial | Industrial | Industrial | Industrial |
주요 차별점
- Highest sample rate in the ADC1010 family at 125 MSPS (vs ADC1010S080HN/C1:5)
- Selectable CMOS or LVDS DDR outputs in one package (vs ADC1010S105HN/C1:5)
- Industrial screening across -40C to +85C (vs ADC1010S065HN/C1:5)
설계 노트
Solder the exposed thermal pad of the 40-HVQFN package to a continuous ground copper pour on the top layer, stitched with at least nine thermal vias to an inner ground plane. This keeps junction temperature within spec at 125 MSPS continuous operation and provides the lowest-impedance return path for analog and digital return currents. Avoid routing signal traces through the thermal pad area - the thermal pad must be a contiguous pour to maintain package solder-joint reliability.
Decouple each analog supply pin (AVDD) with a 100 nF X7R ceramic capacitor placed within 2 mm of the pin, paired with a bulk 10 uF tantalum or ceramic capacitor at the supply entry point. Place the digital supply decoupling (DVDD, OVDD) symmetrically around the output data pins. Estimated: total supply decoupling ESR budget should remain below 50 milliohm at the ADC clock frequency to limit supply ripple below 1 LSB.
When using LVDS DDR output mode, terminate each LVDS pair with a 100 ohm differential resistor at the receiver end (typically inside the FPGA). Floating LVDS pairs will reflect energy back into the ADC output drivers and degrade SNR. In CMOS mode, drive the digital outputs into a tightly impedance-matched transmission line if the trace exceeds approximately 25 mm to prevent ringing on the LSB transitions.
Route the analog input (AIN, AIN_COM) as a 100 ohm differential pair, length-matched within 1 mm and isolated from digital output buses by a ground fence. Keep the clock input trace short and reference it to the analog ground plane to avoid jitter that would degrade SNR. Estimated: each picosecond of clock jitter reduces SNR by approximately 0.5 dB at 125 MSPS, so total CLK jitter must remain below 3 ps RMS.
규정 준수 정보
RoHS and REACH compliance per Renesas product page. Industrial screening level, not AEC-Q100 qualified - this part is not designed for automotive applications.
