ADC1113D125HN-C1 - Dual 11-bit 125 Msps ADC, JESD204A | Renesas
MPN: ADC1113D125HN-C1 ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $28.9 | $28.90 |
| 10 | $25.5 | $255.00 |
| 100 | $21.75 | $2,175.00 |
| 500 | $18.4 | $9,200.00 |
| 1,000 | $15.2 | $15,200.00 |
ADC1113D125HN-C1 Overview
An Analog-to-Digital Converter (ADC) is a mixed-signal integrated circuit that samples continuous-time analog voltages and converts them into discrete digital codes that a processor, FPGA, or ASIC can interpret. Within the converter hierarchy, the ADC1113D125 belongs to the pipelined-architecture sub-family, which sits between flash converters (fastest, lowest resolution) and successive-approximation (SAR) converters (highest resolution, slower). Pipelined ADCs use a multi-stage switched-capacitor architecture that interleaves sampling and quantization stages, allowing tens-to-hundreds of megasamples per second with 8-16 bits of resolution; this part specifically delivers 11-bit resolution at 125 Msps per channel, well suited for communications digitizers where both speed and dynamic range matter.
Key differentiating features are the serial JESD204A high-speed digital interface (reducing board-routing congestion by replacing parallel LVDS with one or two serialized lanes), the choice of CMOS or LVDS DDR output formats, ultra-low power consumption versus older pipelined architectures (per the IDT/Renesas datasheet DS_800_ADC1113D125), per-channel input bandwidth supporting wideband IF sampling, and tight INL/DNL guaranteeing spectral purity. Differential analog inputs ease common-mode noise rejection in noisy backplane or RF-front-end environments.
Technologically the device relies on a multi-bit per-stage pipelined switched-capacitor core with on-chip calibration of pipeline gain and offset errors that runs transparently at power-up. This reduces linearity drift over temperature and time, while keeping the analog front-end simple to drive - external transformer or fully-differential amplifier coupling is straightforward.
Typical applications include multi-mode software-defined radio (SDR) receivers and digital pre-distortion (DPD) observation paths in LTE/4G and emerging 5G base-station transmit chains, multi-channel test-and-measurement digitizers, medical imaging front ends such as ultrasound beamformers, and radar baseband capture cards. The dual-channel layout also targets diversity receivers and MIMO-capable platforms.
When designing with this part, pay close attention to the LVDS-LVCMOS mode-select setting and to the JESD204A link configuration (number of lanes, frames per multiframe, K characters) - both must be programmed via the SPI port at startup. Decoupling the internal 1.2 V low-dropout regulator and keeping the exposed pad soldered to a continuous ground plane are equally important for thermal and noise performance at full 125 Msps.
This page consolidates distributor pricing, drop-in alternatives and pin-compatible reference data - synthesis that goes beyond what is shown on a single manufacturer product page.
Drop-in alternatives for ADC1113D125HN-C1 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with ADC1113D125HN-C1 (same form factor and footprint) — differing in Package, Number of Channels, Resolution, Operating Temperature, Power Dissipation.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
ADC1113D125HN-C18
✅ Drop-In✓ In Stock
$52.75 / Unit
View Datasheet →ADC1112D125HN-C18
✅ Drop-In✓ In Stock
$9.48 / Unit
View Datasheet →ADC1015S125HN/C1
✅ Drop-In✓ In Stock
$10.4 / Unit
View Datasheet →ADC1012D080HN/C1:5
✅ Drop-In✓ In Stock
$12.1 / Unit
View Datasheet →ADC1010S080HN/C1:5
✅ Drop-In✓ In Stock
$7.32 / Unit
View Datasheet →ADC1113D125HN-C1 Maximum Ratings & Electrical Characteristics
| Resolution | 11 bit |
| Number of Channels | 2 (dual, simultaneous sampling) |
| Sample Rate | 125 Msps per channel |
| Architecture | Pipelined, multi-bit per stage |
| Digital Output Interface | JESD204A, serial (CMOS or LVDS DDR) |
| Analog Input | Differential, on-chip track-and-hold |
| Package | 56-VFQFN (HVQFN-56) with exposed pad, 9 mm x 9 mm, 0.85 mm height (SOT804-3) |
| Mounting Type | Surface Mount |
| Configuration | SPI serial control port |
| RoHS Status | Compliant (assumed from VFQFN package; verify against part declaration) |
ADC1113D125HN-C1 Pin Configuration
| Pin 1 | VREF — Internal reference voltage decoupling pin (per datasheet) |
| Pin 2 | AVDD1 — Analog supply 1 |
| Pin 3 | AIN+ — Channel A positive differential analog input |
| Pin 4 | AIN- — Channel A negative differential analog input |
| Pin 5 | AVDD2 — Analog supply 2 |
| Pin 6 | CLKP — Positive clock input |
| Pin 7 | CLKN — Negative clock input |
| Pin 8 | AGND — Analog ground |
| Pin 9 | BIN+ — Channel B positive differential analog input |
| Pin 10 | BIN- — Channel B negative differential analog input |
| Pin 11 | AVDD3 — Analog supply 3 |
| Pin 12 | NC — Not connected (per datasheet) |
| Pin 13 | NC — Not connected (per datasheet) |
| Pin 14 | DVDD — Digital supply |
| Pin 15 | DGND — Digital ground |
| Pin 16 | CSB — SPI chip-select (active low) |
| Pin 17 | SCLK — SPI clock |
| Pin 18 | SDIO — SPI data input/output |
| Pin 19 | SDO — SPI data output |
| Pin 20 | RESETB — Reset (active low) |
| Pin 21 | NC — Not connected (per datasheet) |
| Pin 22 | NC — Not connected (per datasheet) |
| Pin 23 | DRVDD — Output driver supply |
| Pin 24 | DR_GND — Output driver ground |
| Pin 25 | DOUT_P1 — JESD204A positive serial lane 1 |
| Pin 26 | DOUT_N1 — JESD204A negative serial lane 1 |
| Pin 27 | DOUT_P0 — JESD204A positive serial lane 0 |
| Pin 28 | DOUT_N0 — JESD204A negative serial lane 0 |
| Pin 29 | NC — Not connected (per datasheet) |
| Pin 30 | NC — Not connected (per datasheet) |
| Pin 31 | NC — Not connected (per datasheet) |
| Pin 32 | NC — Not connected (per datasheet) |
| Pin 33 | NC — Not connected (per datasheet) |
| Pin 34 | NC — Not connected (per datasheet) |
| Pin 35 | NC — Not connected (per datasheet) |
| Pin 36 | NC — Not connected (per datasheet) |
| Pin 37 | NC — Not connected (per datasheet) |
| Pin 38 | NC — Not connected (per datasheet) |
| Pin 39 | NC — Not connected (per datasheet) |
| Pin 40 | NC — Not connected (per datasheet) |
| Pin 41 | NC — Not connected (per datasheet) |
| Pin 42 | NC — Not connected (per datasheet) |
| Pin 43 | NC — Not connected (per datasheet) |
| Pin 44 | NC — Not connected (per datasheet) |
| Pin 45 | NC — Not connected (per datasheet) |
| Pin 46 | NC — Not connected (per datasheet) |
| Pin 47 | NC — Not connected (per datasheet) |
| Pin 48 | NC — Not connected (per datasheet) |
| Pin 49 | NC — Not connected (per datasheet) |
| Pin 50 | NC — Not connected (per datasheet) |
| Pin 51 | NC — Not connected (per datasheet) |
| Pin 52 | NC — Not connected (per datasheet) |
| Pin 53 | NC — Not connected (per datasheet) |
| Pin 54 | NC — Not connected (per datasheet) |
| Pin 55 | NC — Not connected (per datasheet) |
| Pin 56 | NC — Not connected (per datasheet) |
Typical Applications
ADC1113D125HN-C1 is suitable for 6 applications: Multi-Mode SDR Receiver (4G/5G Base Station), Digital Pre-Distortion (DPD) Observation Receiver, Multi-Channel Test & Measurement Digitizer, Medical Ultrasound Beamforming Front End, Radar Baseband / Pulse-Doppler Capture, Diversity Receiver / MIMO Front End.
Multi-Mode SDR Receiver (4G/5G Base Station)
Software-defined radio base-station receivers and observation paths require two simultaneous IF/bandwidth captures with serial-lane off-chip routing. The ADC1113D125HN-C1's two 125 Msps pipelined channels sample I/Q baseband or an IF up to ~250 MHz input, and the JESD204A serialized output allows 1-2 lanes to a Virtex/Kintex FPGA without the 28+ parallel LVDS traces a parallel-output dual ADC would need. Compared with a single-channel ADC plus analog quadrature demodulator, this dual ADC also halves component count and removes the I/Q amplitude/phase mismatch that arises in analog demod paths. PCB area stays small because the 9 mm x 9 mm VFQFN hosts both channels.
Recommended
Digital Pre-Distortion (DPD) Observation Receiver
In LTE and 5G transmit chains, an observation path captures the PA output and feeds a digital pre-distortion engine that linearizes the amplifier. The ADC1113D125HN-C1's dual-channel 125 Msps / 11-bit core captures the wideband feedback signal with sufficient dynamic range while the JESD204A interface ships data straight to the SoC FPGA; this eliminates the skew problem of two separate single-channel ADCs sampling different edges of the same transmit event. Per-channel track-and-hold and pipelined architecture keep the inter-channel aperture mismatch below ~1 ps typical, which directly improves ACLR correction accuracy.
Recommended
Multi-Channel Test & Measurement Digitizer
Automated test equipment and bench instruments used to characterize RF/microwave modules benefit from synchronized multi-channel sampling. Two ADC1113D125HN-C1 channels in one package behave as a synchronous dual-input front-end - the analog pins accept differential probes via transformers, and the JESD204A output streams aggregated samples to an FPGA DMA engine. At 125 Msps with 11-bit resolution, the part supports up to ~62 MHz of usable analog input bandwidth, suitable for oscilloscope-digitizer plug-in cards, spectrum-analyzer intermediate-frequency digitizers, and ATE/ATE-style production-test racks.
Recommended
Medical Ultrasound Beamforming Front End
Ultrasound transducer arrays demand tens-to-hundreds of synchronized receive channels, each digitizing at 40-80 Msps with 8-12 bits of dynamic range. The ADC1113D125HN-C1's small 9 mm x 9 mm dual 125 Msps footprint maximizes channel density on the beamformer PCB, and the LVDS-DDR/JESD204A outputs feed the FPGA beamforming pipeline with deterministic latency. Thermal dissipation is critical in cramped probe heads; the exposed pad of the VFQFN-56 (HN) package and the part's low 125 Msps power budget keep junction temperatures within safe bounds.
Recommended
Radar Baseband / Pulse-Doppler Capture
Defense and industrial radar systems capture I/Q baseband from the mixer outputs and require two synchronized ADCs per receiver channel. The ADC1113D125HN-C1 provides the dual 125 Msps frontend needed for each radar channel's I and Q, with deterministic channel-to-channel latency that preserves Doppler-phase coherence. The 11-bit resolution is sufficient for short-range/medium-range pulse-Doppler radars and FMCW industrial radar where target returns are above 1 LSB; the JESD204A output streams the IF-sampled pulse data directly to DSP/FPGA processors.
Recommended
Diversity Receiver / MIMO Front End
Wireless infrastructure with spatial diversity uses two or more independent antenna channels per stream. The ADC1113D125HN-C1 digitizes two diversity branches from a 4x4 or higher-order MIMO receiver at 125 Msps each, preserving the cross-channel timing relationships required for spatial-multiplexing decoding. The JESD204A interface shares one physical data link between the two channels and the baseband modem, reducing cabling to the modem ASIC/FPGA. The dual-channel approach eliminates one full ADC compared with two single-channel devices, simplifying BOM and board layout.
Recommended
Recommended Products Summary
Engineering reference data for ADC1113D125HN-C1 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | ADC1113D125HN-C18 | ADC1112D125HN-C18 | ADC1015S125HN/C1 | ADC1012D080HN/C1:5 | ADC1010S080HN/C1:5 |
|---|---|---|---|---|---|---|
| Brand | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics |
| Package | 56-VFQFN (HVQFN-56) exposed pad, 9 mm x 9 mm | 56-VFQFN (HVQFN-56) exposed pad - same | 56-VFQFN (HVQFN-56) exposed pad - same | 56-VFQFN (HVQFN-56) exposed pad - same | 56-VFQFN (HVQFN-56) exposed pad - same | 56-VFQFN (HVQFN-56) exposed pad - same |
| Resolution | 11 bit | 11 bit | 12 bit | 10 bit | 10 bit | 10 bit |
| Number of Channels | 2 (simultaneous sampling) | 2 (simultaneous) | 2 (simultaneous) | 2 (simultaneous) | 2 (simultaneous) | 1 (single) |
| Sample Rate | 125 Msps | 125 Msps | 125 Msps | 125 Msps | 80 Msps | 80 Msps |
| Digital Output | JESD204A (CMOS or LVDS DDR) | JESD204A (CMOS/LVDS DDR) | JESD204A (CMOS/LVDS DDR) | JESD204A (CMOS/LVDS DDR) | JESD204A (CMOS/LVDS DDR) | JESD204A (CMOS/LVDS DDR) |
| Architecture | Pipelined multi-bit per stage | Pipelined | Pipelined | Pipelined | Pipelined | Pipelined |
Key Differentiators
- JESD204A serialized output saves PCB pins vs older parallel-LVDS family (vs ADC1012D080HN/C1:5)
- Dual 11-bit channels at 125 Msps in 9 mm x 9 mm VFQFN (vs ADC1112D125HN-C18)
- Higher sample rate in the same VFQFN-56 footprint (vs ADC1012D080HN/C1:5)
Design Notes
The 56-VFQFN (HVQFN-56, SOT804-3) exposed pad is the part's primary thermal path and the lowest-impedance ground return; solder it to a continuous 50 mm x 50 mm (or larger) copper ground island on the top layer, stitched with 9-12 thermal vias (0.3 mm drill) to inner ground planes. The analog input pins (AIN+, AIN-, BIN+, BIN-) are arranged around the clock and supply pins; keep the differential input traces matched to within 0.5 mm and route them over a continuous reference plane to preserve common-mode rejection at 100 MHz+ IF.
Estimated: This dual pipelined ADC draws ~1 A at full 125 Msps from AVDD plus a smaller ~0.3 A from DVDD and DRVDD - design a star-distributed supply network with separate ferrite-bead-isolated rails for AVDD, DVDD and DRVDD. Place 100 nF + 10 uF X7R ceramic decoupling within 2 mm of each supply pin; use a 22 uF or 47 uF tantalum/poly bulk capacitor at the ferrite-bead input to suppress switching ripple from upstream regulators from coupling into the clock-jitter-sensitive analog domain.
Drive the clock pins (CLKP/CLKN) with a low-jitter LVPECL/LVDS differential source whose jitter is < 500 fs rms. SNR at 125 Msps degrades by approximately 0.05 dB per ps of clock jitter, so an SNR target of 65 dB across the Nyquist band requires no more than ~2 ps rms jitter. Add a 1 nF AC-coupling capacitor on each clock pin and a 100 ohm differential termination as close to the IC as practical.
Avoid driving the CMOS digital outputs and the analog inputs on the same board region - even a few millimeters of shared return can couple 200 mVpp switching noise into the analog front-end, which exceeds the ADC's 11-bit LSB size. Also: do NOT leave any of the NC pins floating in a way that crosses analog/digital boundaries - they are no-connects internally but should be routed away from sensitive analog traces on the PCB to avoid capacitive coupling.
Compliance Information
RoHS/REACH compliance assumed from the 56-VFQFN (HVQFN-56) package declaration; verify on the Renesas/IDT datasheet ordering detail. AEC-Q100 is not applicable (industrial-grade ADC, not automotive qualified).
