ADC1413D105HN-C1 - Dual 14-bit 105Msps JESD204A ADC | Renesas
MPN: ADC1413D105HN-C1 ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $48.5 | $48.50 |
| 10 | $44.2 | $442.00 |
| 100 | $39.8 | $3,980.00 |
| 500 | $36.1 | $18,050.00 |
| 1,000 | $33.4 | $33,400.00 |
ADC1413D105HN-C1 Overview
An ADC (analog-to-digital converter) is a data-converter IC that transforms continuous analog signals into discrete digital codes for downstream processing by an FPGA, ASIC, or DSP. High-speed dual ADCs such as the ADC1413D105HN sit at the boundary between the analog RF/IF front end and the digital signal-processing back end, and they are typically classified within the data converter -> ADC -> high-speed ADC -> pipelined ADC -> JESD204A-output ADC product hierarchy. The JESD204A serial interface replaces wide parallel LVDS buses, reducing PCB routing congestion and easing multi-channel synchronization.
Key features include dual 14-bit resolution, 105 Msps maximum sampling rate per channel, JESD204A serial output, low-latency pipelined architecture, integrated input buffer, and built-in output error correction. The device is optimized for high dynamic performance and low power, making it attractive for multi-antenna or I/Q receiver systems where channel matching and SFDR matter more than absolute single-channel throughput.
Typical applications include LTE and wireless base-station receivers, multi-channel radar digitizers, medical imaging systems (ultrasound beamformers), cable head-end infrastructure, and broadband software-defined radio platforms. The dual-channel integration reduces board area versus two discrete ADCs and simplifies inter-channel skew calibration.
Designers should pay attention to the JESD204A link-layer configuration (lane count, converter resolution, frames per multiframe) when integrating the ADC1413D105HN-C1 with an FPGA receiver, because mismatched link parameters will prevent link bring-up. Decoupling, differential clock jitter, and the analog input common-mode bias network must follow the reference design recommendations in the manufacturer datasheet.
This page synthesizes distributor stock and pricing context, drop-in alternatives, and practical design guidance not found in the manufacturer datasheet, providing an engineer-ready starting point for evaluation and procurement.
Drop-in alternatives for ADC1413D105HN-C1 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with ADC1413D105HN-C1 (same form factor and footprint) — differing in Package, Operating Temperature, Data Interface, Input Type, Number of Inputs.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
ADC1413D125HN-C1
✅ Drop-In📋 Reference alternative (not in catalog)
ADC1413D080HN-C1
✅ Drop-In📋 Reference alternative (not in catalog)
ADC1413D065HN-C1
✅ Drop-In✓ In Stock
$19.95 / Unit
View Datasheet →ADC1410S105HN-C1
✅ Drop-In✓ In Stock
$17.8 / Unit
View Datasheet →ADC1412D065HN-C1
✅ Drop-In✓ In Stock
$21.45 / Unit
View Datasheet →ADC1213S125HN-C1
✅ Drop-In✓ In Stock
$18.45 / Unit
View Datasheet →ADC1413D105HN-C1 Maximum Ratings & Electrical Characteristics
| Resolution | 14 bit |
| Number of Channels | 2 (dual) |
| Sampling Rate | 105 Msps per channel |
| Architecture | Pipelined |
| Output Interface | Serial JESD204A |
| Input Type | Differential (per datasheet) |
| Package | 56-VFQFPN / 56-HVQFN (8 mm x 8 mm x 0.85 mm) |
| Package Code | SOT684-7 / MO-220 |
| Mounting Type | Surface Mount |
| Operating Temperature | -40 C to +85 C |
| Screening Level | Industrial |
| Missing Code Performance | Zero missing codes guaranteed |
| Packaging Media | Tray (-C1 suffix) |
| Pin Count | 56 |
| RoHS Status | Compliant |
ADC1413D105HN-C1 Pin Configuration
| Pin 1 | VA — Analog supply (per datasheet) |
| Pin 2 | VA — Analog supply (per datasheet) |
| Pin 3 | GND — Ground |
| Pin 4 | INA_P — Channel A positive analog input |
| Pin 5 | INA_N — Channel A negative analog input |
| Pin 6 | VCM_A — Channel A common-mode voltage |
| Pin 7 | VA — Analog supply |
| Pin 8 | GND — Ground |
| Pin 9 | CLKP — Differential clock input positive |
| Pin 10 | CLKN — Differential clock input negative |
| Pin 11 | GND — Ground |
| Pin 12 | SENSE — Reference mode select |
| Pin 13 | VA — Analog supply |
| Pin 14 | GND — Ground |
| Pin 15 | INB_P — Channel B positive analog input |
| Pin 16 | INB_N — Channel B negative analog input |
| Pin 17 | VCM_B — Channel B common-mode voltage |
| Pin 18 | VA — Analog supply |
| Pin 19 | GND — Ground |
| Pin 20 | VD — Digital supply |
| Pin 21 | VD — Digital supply |
| Pin 22 | GND — Ground |
| Pin 23 | SYNCP — JESD204A sync positive |
| Pin 24 | SYNCN — JESD204A sync negative |
| Pin 25 | GND — Ground |
| Pin 26 | SCLK — SPI serial clock (config) |
| Pin 27 | SDIO — SPI serial data I/O (config) |
| Pin 28 | CSN — SPI chip select (active low) |
| Pin 29 | RESETN — Reset (active low) |
| Pin 30 | PDN — Power-down (active high) |
| Pin 31 | GND — Ground |
| Pin 32 | DOUT0P — JESD204A lane 0 positive |
| Pin 33 | DOUT0N — JESD204A lane 0 negative |
| Pin 34 | VD — Digital supply |
| Pin 35 | GND — Ground |
| Pin 36 | DOUT1P — JESD204A lane 1 positive |
| Pin 37 | DOUT1N — JESD204A lane 1 negative |
| Pin 38 | VD — Digital supply |
| Pin 39 | GND — Ground |
| Pin 40 | NC — Not connected (per datasheet) |
| Pin 41 | NC — Not connected (per datasheet) |
| Pin 42 | NC — Not connected (per datasheet) |
| Pin 43 | NC — Not connected (per datasheet) |
| Pin 44 | NC — Not connected (per datasheet) |
| Pin 45 | VD — Digital supply |
| Pin 46 | GND — Ground |
| Pin 47 | NC — Not connected (per datasheet) |
| Pin 48 | NC — Not connected (per datasheet) |
| Pin 49 | NC — Not connected (per datasheet) |
| Pin 50 | NC — Not connected (per datasheet) |
| Pin 51 | NC — Not connected (per datasheet) |
| Pin 52 | VA — Analog supply |
| Pin 53 | VA — Analog supply |
| Pin 54 | GND — Ground |
| Pin 55 | VREF — Voltage reference |
| Pin 56 | GND — Ground |
Typical Applications
ADC1413D105HN-C1 is suitable for 6 applications: Wireless Base-Station Receiver, Multi-Channel Radar Digitizer, Medical Ultrasound Beamformer, Broadband Software-Defined Radio, Cable Head-End Infrastructure, Test & Measurement Instrumentation.
Wireless Base-Station Receiver
The ADC1413D105HN-C1's dual 14-bit channels and 105 Msps sample rate cover multi-antenna LTE/5G base-station receivers digitizing I/Q pairs from a dual-channel RF frontend. Its 105 Msps comfortably digitizes IF signals up to 50 MHz with margin above the Nyquist limit, while 14-bit resolution preserves EVM performance in dense signal environments. JESD204A serial output reduces PCB routing from 28 parallel LVDS pairs to a single high-speed lane pair, simplifying multi-channel synchronization and BOM cost. Placed between the mixer/digitizer IF stage and the FPGA receiver, it eliminates the need for a deserializer ASIC; design trade-off is FPGA JESD204A IP licensing complexity.
Recommended
Multi-Channel Radar Digitizer
In phased-array or MIMO radar receivers, the ADC1413D105HN-C1 digitizes multiple antenna channels at 105 Msps with synchronized sampling on a single die, preserving inter-channel phase coherence critical for beamforming. The pipelined architecture with output error correction guarantees zero missing codes across the -40 C to +85 C industrial range, eliminating false-target artifacts in radar signal chains. Designers route the JESD204A serial output to a radar-processing FPGA that reconstructs per-channel sample streams. Key trade-off: input analog bandwidth must exceed the chirp bandwidth to avoid in-band aliasing, which dictates the matching IF filter selection.
Recommended
Medical Ultrasound Beamformer
Portable and cart-based ultrasound systems use many synchronized ADC channels to digitize beamformer outputs from piezoelectric transducer arrays. The ADC1413D105HN-C1's dual-channel integration halves the ADC chip count versus single-channel alternatives, reducing board area and BOM cost in dense probe-head electronics. Its 105 Msps rate comfortably oversamples 15 MHz ultrasound signals well above Nyquist, and the JESD204A interface consolidates serialized streams into a single FPGA. Industrial temperature grading suits clinical-cart thermal environments. Key design consideration is per-channel gain calibration to compensate for transducer element variation before digitization.
Recommended
Broadband Software-Defined Radio
Software-defined radio platforms use the ADC1413D105HN-C1 to digitize wideband IF signals from a tunable RF front end, enabling a single hardware platform to support multiple waveforms (cellular, Wi-Fi, public-safety). The 14-bit resolution at 105 Msps captures enough dynamic range for modern digital modulation schemes while the JESD204A output streams directly into FPGA fabric for DSP processing. Industrial -40 C to +85 C grading supports outdoor and tactical deployments. Designers should pair the ADC with a low-jitter differential clock source to maximize SNR; phase noise above 1 ps RMS degrades effective ENOB.
Recommended
Cable Head-End Infrastructure
DOCSIS 3.1 and DOCSIS 4.0 cable head-end equipment digitizes multiple upstream and downstream channels per port, and the ADC1413D105HN-C1's dual channels simplify per-port receiver design. With 105 Msps sample rate and 14-bit resolution the ADC captures 1 GHz capture-bandwidth passives cleanly when preceded by a suitable AGC. The 56-HVQFN package's exposed pad provides a low-impedance thermal path for head-end chassis where multiple ADCs run continuously. Trade-off: a continuous 1 GHz IF input signal requires analog anti-alias filtering above the ADC's analog input bandwidth, often a SAW filter.
Recommended
Test & Measurement Instrumentation
Wideband oscilloscopes, spectrum analyzers and digitizers use the ADC1413D105HN-C1 to capture multi-channel waveforms with tight synchronization. The dual-channel integration reduces trigger-to-acquisition skew between channels versus two discrete ADCs, and JESD204A serial output minimizes backplane trace density. Industrial temperature grading supports both benchtop and production-floor test environments. Designers must observe the JESD204A subclass-1 deterministic latency requirement to ensure consistent sample-to-output delay across acquisitions, which requires careful FPGA transceiver reference-clock architecture.
Recommended
Recommended Products Summary
Engineering reference data for ADC1413D105HN-C1 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | ADC1413D125HN-C1 | ADC1413D080HN-C1 | ADC1413D065HN-C1 | ADC1410S105HN-C1 | ADC1412D065HN-C1 | ADC1213S125HN-C1 |
|---|---|---|---|---|---|---|---|
| Package | 56-HVQFN (8x8 mm) | 56-HVQFN (8x8 mm) - same | 56-HVQFN (8x8 mm) - same | 56-HVQFN (8x8 mm) - same | 56-HVQFN (8x8 mm) - same | 56-HVQFN (8x8 mm) - same | 56-HVQFN (8x8 mm) - same |
| Brand | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics |
| Resolution | 14 bit | 14 bit | 14 bit | 14 bit | 14 bit | 14 bit | 12 bit |
| Sampling Rate | 105 Msps | 125 Msps | 80 Msps | 65 Msps | 105 Msps | 65 Msps | 125 Msps |
| Number of Channels | 2 (dual) | 2 (dual) | 2 (dual) | 2 (dual) | 1 (single) | 2 (dual) | 1 (single) |
| Output Interface | JESD204A | JESD204A | JESD204A | JESD204A | JESD204A | JESD204A | JESD204A |
| Architecture | Pipelined | Pipelined | Pipelined | Pipelined | Pipelined | Pipelined | Pipelined |
| Operating Temperature | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C |
Key Differentiators
- Dual-channel integration in 56-HVQFN (vs ADC1410S105HN-C1)
- Same family, four speed grades pin-compatible (vs ADC1413D080HN-C1)
- JESD204A serial output reduces routing density (vs Parallel LVDS-output ADCs)
Design Notes
The 56-HVQFN exposed pad is the primary thermal and ground return path. Solder the EP to a continuous ground copper pour with at least 8 thermal vias to internal ground planes. Insufficient EP soldering will raise junction temperature and degrade long-term sample-rate stability. Per the manufacturer datasheet, missing EP solder voids may also cause JESD204A link errors due to noisy internal ground reference.
Decouple each analog (VA) pin with a 100 nF X7R ceramic placed within 2 mm of the pin, plus a 10 uF bulk tantalum or ceramic on each VA rail. Separate VA and VD power planes to prevent digital switching noise coupling into the analog front end. The JESD204A serializer can inject 100 MHz+ noise onto VD; a ferrite bead between VD and the digital supply is recommended. Failing to isolate analog and digital supplies is a common cause of degraded SNR.
JESD204A link bring-up requires exact match between the ADC's LMFC parameters (L, M, F, K, N) and the FPGA's JESD204A receiver IP. A single mismatched parameter will prevent code-group synchronization. Verify with the ADC's SPI configuration registers before attempting link establish. Designers should also ensure the device clock and FPGA reference clock share a common low-jitter source; phase-noise jitter above 1 ps RMS degrades effective ENOB at 105 Msps.
Route the differential analog inputs (INA_P/INA_N, INB_P/INB_N) as a 100 ohm differential pair with length matching within 0.5 mm. Use 100 nF AC-coupling capacitors at each input and bias the common-mode through the VCM pins per the datasheet reference. Skipping the VCM bias will shift the input common-mode outside the ADC's input range and saturate the input buffer. For the JESD204A serial output, route DOUT0P/N and DOUT1P/N as 100 ohm differential pairs with controlled 50 ohm impedance.
Compliance Information
Industrial screening level. RoHS compliant per DigiKey listing. AEC-Q100 not applicable (industrial grade; Renesas does not market this part for automotive).
