ADS1299IPAGR - 8-Ch 24-Bit AFE for EEG/Biopotential | Texas Instruments
MPN: ADS1299IPAGR ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $38.5 | $38.50 |
| 10 | $35.1 | $351.00 |
| 100 | $31.2 | $3,120.00 |
| 500 | $27.85 | $13,925.00 |
| 1,000 | $24.6 | $24,600.00 |
| 3,000 | $22.1 | $66,300.00 |
ADS1299IPAGR Overview
An analog front end (AFE) is an integrated circuit that combines a low-noise analog signal chain (typically PGA, filters, and ADC reference) with the digitizing converter on a single die. The ADS1299 belongs to the broader hierarchy of mixed-signal data converters, then successive-approximation or delta-sigma ADCs, and finally precision measurement ICs that interface directly with low-amplitude physiological sensors. By integrating the biasing, lead-off detection, and right-leg drive drivers required for EEG/ECG/EMG, the AFE reduces the external component count compared to a discrete ADC-plus-op-amp solution.
Key features include a PGA with gains from 1 to 24 in 7 steps, internal 4.5 V low-drift reference (30 ppm/C typical), internal oscillator, and selectable SPI-compatible serial interface. Input common-mode rejection exceeds 110 dB at 60 Hz, and the integrated bias amplifier supplies patient or subject bias in active electrode circuits. Power consumption is approximately 42 mW per channel with all channels active, while a flexible power-down mode reduces current to microamp levels for wearable battery-powered applications.
Architecturally, the device uses a chopper-stabilized, multi-bit delta-sigma modulator per channel followed by a digital decimation filter. This topology achieves the very low input-referred noise necessary for sub-microvolt biopotential signals while suppressing 1/f and mains interference. The internal reference and oscillator eliminate two critical external components that typically drift across temperature in discrete designs.
Typical applications include electroencephalography (EEG) headsets, polysomnography and sleep monitoring, electrocardiography (ECG/Holter) patient monitors, electromyography (EMG) prosthetics, brain-computer interfaces (BCI), and electrophysiology research instrumentation. In EEG systems the part's CMRR and noise floor allow detection of microvolt-scale cortical signals without complex shielding.
When designing with the ADS1299, place the device on a four-layer PCB with a continuous analog ground plane, route the analog inputs as guarded differential pairs, and use a clean low-noise LDO such as the TPS7A4701 for AVDD to preserve noise performance. Always refer to the manufacturer datasheet and the ADS1299 evaluation module (ADS1299EEGFE-PDK) reference design for layout guidance.
Drop-in alternatives for ADS1299IPAGR — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with ADS1299IPAGR (same form factor and footprint) — differing in Input-Referred Noise, Internal Reference, Package, Number of Channels, Operating Temperature.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
ADS1299IPAG
✅ Drop-In📋 Reference alternative (not in catalog)
ADS1299IPAGRG4
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
ADS1299-6PAG
✅ Drop-In✓ In Stock
$22.05 / Unit
View Datasheet →ADS1299-4PAG
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
ADS1298IPAG
✅ Drop-In✓ In Stock
$24.5 / Unit
View Datasheet →ADS1299IPAGR Maximum Ratings & Electrical Characteristics
| Number of Channels | 8 |
| Resolution | 24 bit |
| Architecture | Delta-Sigma (Delta Sigma) |
| Sampling Rate | 16 kSPS per channel (max) |
| PGA Gain Range | 1x to 24x (7 steps) |
| Input-Referred Noise | 0.5 uVpp typical (gain = 24, data rate 250 SPS) |
| Common-Mode Rejection Ratio (CMRR) | 110 dB at 60 Hz |
| Internal Reference | 4.5 V, 30 ppm/C drift |
| Supply Voltage (AVDD) | 5 V (analog supply) |
| Supply Voltage (DVDD) | 1.8 V to 3.6 V (digital supply) |
| Power Dissipation | 42 mW per channel |
| Operating Temperature | -40C to +85C |
| Package | 64-TQFP (PAG) 10x10 mm |
| Interface | SPI-compatible serial |
| On-chip Features | Bias amplifier, lead-off detection, right-leg drive, internal oscillator |
| Mounting Type | Surface Mount |
| MSL Level | 3 (168 hours) |
| RoHS Status | Compliant |
ADS1299IPAGR Pin Configuration
| Pin 1 | AVDD — Analog supply (5 V typical) |
| Pin 2 | AVSS — Analog ground |
| Pin 3 | IN1P — Positive input, channel 1 |
| Pin 4 | IN1N — Negative input, channel 1 |
| Pin 5 | DVDD — Digital supply (1.8 V to 3.6 V) |
| Pin 6 | IN2P — Positive input, channel 2 |
| Pin 7 | IN2N — Negative input, channel 2 |
| Pin 8 | IN3P — Positive input, channel 3 |
| Pin 9 | IN3N — Negative input, channel 3 |
| Pin 10 | IN4P — Positive input, channel 4 |
| Pin 11 | IN4N — Negative input, channel 4 |
| Pin 12 | AVSS — Analog ground |
| Pin 13 | AVDD1 — Charge-pump analog supply |
| Pin 14 | VCAP1 — Charge-pump capacitor pin 1 |
| Pin 15 | VCAP2 — Charge-pump capacitor pin 2 |
| Pin 16 | AVSS — Analog ground |
| Pin 17 | AVDD — Analog supply (5 V typical) |
| Pin 18 | AVSS — Analog ground |
| Pin 19 | IN5P — Positive input, channel 5 |
| Pin 20 | IN5N — Negative input, channel 5 |
| Pin 21 | IN6P — Positive input, channel 6 |
| Pin 22 | IN6N — Negative input, channel 6 |
| Pin 23 | IN7P — Positive input, channel 7 |
| Pin 24 | IN7N — Negative input, channel 7 |
| Pin 25 | AVSS — Analog ground |
| Pin 26 | RL — Right-leg drive output |
| Pin 27 | BIAS — Bias amplifier output |
| Pin 28 | BIASIN — Bias amplifier input |
| Pin 29 | AVDD — Analog supply (5 V typical) |
| Pin 30 | AVSS — Analog ground |
| Pin 31 | IN8P — Positive input, channel 8 |
| Pin 32 | IN8N — Negative input, channel 8 |
| Pin 33 | TESTP — Test signal positive input |
| Pin 34 | TESTN — Test signal negative input |
| Pin 35 | AVSS — Analog ground |
| Pin 36 | VCAP3 — Decoupling capacitor pin 3 |
| Pin 37 | AVSS — Analog ground |
| Pin 38 | AVDD — Analog supply (5 V typical) |
| Pin 39 | AVSS — Analog ground |
| Pin 40 | VCAP4 — Decoupling capacitor pin 4 |
| Pin 41 | AVDD — Analog supply (5 V typical) |
| Pin 42 | AVSS — Analog ground |
| Pin 43 | GPIO1 — General-purpose IO 1 |
| Pin 44 | DVDD — Digital supply (1.8 V to 3.6 V) |
| Pin 45 | DGND — Digital ground |
| Pin 46 | CLKSEL — Clock select (internal/external) |
| Pin 47 | PWDN — Power-down input (active low) |
| Pin 48 | RESET — Reset input (active low) |
| Pin 49 | CS — SPI chip select (active low) |
| Pin 50 | SCLK — SPI serial clock |
| Pin 51 | DIN — SPI serial data input |
| Pin 52 | DOUT — SPI serial data output |
| Pin 53 | DRDY — Data ready output (active low) |
| Pin 54 | GPIO2 — General-purpose IO 2 |
| Pin 55 | GPIO3 — General-purpose IO 3 |
| Pin 56 | GPIO4 — General-purpose IO 4 |
| Pin 57 | DGND — Digital ground |
| Pin 58 | CLK — External clock input (optional) |
| Pin 59 | AVSS — Analog ground |
| Pin 60 | AVDD — Analog supply (5 V typical) |
| Pin 61 | AVSS — Analog ground |
| Pin 62 | VCAP5 — Decoupling capacitor pin 5 |
| Pin 63 | AVSS — Analog ground |
| Pin 64 | AVDD — Analog supply (5 V typical) |
Typical Applications
ADS1299IPAGR is suitable for 6 applications: Electroencephalography (EEG) Headsets, Polysomnography and Sleep Monitoring, Electrocardiography (ECG/Holter) Patient Monitors, Brain-Computer Interface (BCI) Hardware, Electromyography (EMG) Prosthetics, Research Electrophysiology Instrumentation.
Electroencephalography (EEG) Headsets
The ADS1299IPAGR is the de facto industry-standard AFE for research-grade EEG headsets and brain-computer interfaces. Its 0.5 uVpp input-referred noise at gain = 24 and 110 dB CMRR at 60 Hz allow detection of sub-microvolt cortical signals without complex shielding, while 8 differential channels natively support 10-20 system montages. The integrated right-leg drive amplifier drives the common-mode voltage back to the subject to actively suppress mains interference, eliminating a discrete op-amp circuit. Placed between Ag/AgCl scalp electrodes and a host MCU, the part's 42 mW per channel power budget stays manageable on lithium-ion powered wireless headsets.
Recommended
Polysomnography and Sleep Monitoring
Polysomnography systems combine EEG, EOG, EMG and ECG channels, and the ADS1299IPAGR's 8 differential inputs can serve multiple signal chains from a single device. Its 16 kSPS per channel maximum data rate captures high-frequency neural spikes for sleep-stage scoring, while the internal 4.5 V reference with 30 ppm/C drift keeps the calibration stable across the long recording durations typical of overnight studies. Lead-off detection identifies disconnected electrodes during unattended home sleep tests. Compared to multi-ADC discrete designs, the integrated PGA + ADC + bias amplifier cut board area by roughly 60 percent and simplify regulatory certification.
Recommended
Electrocardiography (ECG/Holter) Patient Monitors
Clinical ECG monitors and Holter recorders benefit from the ADS1299IPAGR's high CMRR (110 dB at 60 Hz) to reject mains hum from skin electrodes. With 8 channels the device can monitor multiple chest leads plus limb electrodes from a single chip, simplifying patient-cable management and reducing BOM cost. The internal bias amplifier and right-leg drive circuitry improve signal quality without external op-amps. At 42 mW per channel the device is appropriate for AC-powered bedside monitors and for battery-powered Holter recorders operating from a 3.7 V Li-ion cell through a step-up converter.
Recommended
Brain-Computer Interface (BCI) Hardware
Brain-computer interface research platforms rely on the ADS1299IPAGR's combination of high channel count, low noise, and simultaneous sampling to decode neural activity for cursor control, prosthetic command, or research telemetry. Simultaneous sampling eliminates inter-channel skew that would distort evoked-response waveforms, while the 0.5 uVpp noise floor resolves single-unit and multi-unit firing patterns at the scalp. The 64-TQFP (PAG) footprint fits within compact wearable BCI rigs, and the SPI interface streams all 8 channels to an FPGA at data rates up to 128 kSPS aggregate.
Recommended
Electromyography (EMG) Prosthetics
Modern myoelectric prosthetic arms decode surface EMG signals from up to 8 forearm muscle sites, which is a perfect fit for the ADS1299IPAGR's 8 differential channels. The integrated PGA with up to 24x gain amplifies the sub-millivolt EMG signals before digitization, eliminating external instrumentation amplifiers. The 16 kSPS per channel rate captures the high-frequency content of muscle contractions needed for proportional motor control. Power dissipation of 42 mW per channel permits battery-powered designs lasting a full day on a small Li-ion cell.
Recommended
Research Electrophysiology Instrumentation
University and pharmaceutical electrophysiology rigs use the ADS1299IPAGR as a flexible front end for cell-based assays, microelectrode array recordings, and patch-clamp signal conditioning. The wide PGA gain range (1 to 24) supports both large extracellular spike signals and small field potentials, while the internal 4.5 V reference keeps calibration stable across long multi-hour experiments. SPI connectivity lets researchers pair the part with an FPGA or data-acquisition card for streaming raw waveforms at full 16 kSPS per channel rate without data loss.
Recommended
Recommended Products Summary
Engineering reference data for ADS1299IPAGR — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | ADS1299IPAG | ADS1299IPAGRG4 | ADS1299-6PAG | ADS1299-4PAG | ADS1298IPAG |
|---|---|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | 64-TQFP (PAG) | 64-TQFP (PAG) | 64-TQFP (PAG) | 64-TQFP (PAG) | 64-TQFP (PAG) | 64-TQFP (PAG) |
| Number of Channels | 8 | 8 | 8 | 6 | 4 | 8 |
| Resolution | 24 bit | 24 bit | 24 bit | 24 bit | 24 bit | 24 bit |
| Input-Referred Noise | 0.5 uVpp | 0.5 uVpp | 0.5 uVpp | 0.5 uVpp | 0.5 uVpp | 1.0 uVpp (typical) |
| CMRR @ 60 Hz | 110 dB | 110 dB | 110 dB | 110 dB | 110 dB | 105 dB |
| Max Data Rate | 16 kSPS/ch | 16 kSPS/ch | 16 kSPS/ch | 16 kSPS/ch | 16 kSPS/ch | 32 kSPS/ch |
| PGA Gain Range | 1 to 24 | 1 to 24 | 1 to 24 | 1 to 24 | 1 to 24 | 1 to 12 |
| Operating Temperature | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C |
Key Differentiators
- Lowest input-referred noise in TI's biopotential AFE family (vs ADS1298IPAG)
- Wider PGA gain range than the ADS1298 (vs ADS1298IPAG)
- Pin-compatible family allowing channel-count flexibility (vs ADS1299-6PAG and ADS1299-4PAG)
- Integrated bias amplifier and right-leg drive eliminate external op-amps (vs Discrete ADC + INA + op-amp front end)
Design Notes
Power the AVDD rail from an ultra-low-noise LDO such as the Texas Instruments TPS7A4701 (4.17 uVrms, 72 dB PSRR at 1 kHz) rather than a switching converter. A 100 nF X7R bypass placed within 3 mm of each AVDD pin and a 10 uF bulk capacitor on the AVSS side reduces switching noise coupling. DVDD may be derived from any low-noise 1.8 V to 3.6 V LDO; the part tolerates separate analog and digital supplies for isolation.
Use a four-layer PCB with a continuous uninterrupted analog ground plane on layer 2 below the IC; avoid routing digital signals across the analog ground island. Route each differential input pair (INxP, INxN) as a tightly coupled guarded pair with characteristic impedance of 50 ohms. Keep the right-leg drive (RL) and bias (BIAS) traces short and surrounded by ground pours to prevent parasitic capacitance from destabilizing the loop. Refer to TI's ADS1299EEGFE-PDK reference design for the recommended layout.
Do not leave VCAP1 through VCAP5 floating; each requires a 1 uF X7R capacitor to AVSS to stabilize the internal charge pump. Failing to populate these caps will result in unstable internal rails and degraded CMRR. Also, do not exceed 5.5 V on AVDD or 3.6 V on DVDD; the absolute maximum ratings per the datasheet are 6.0 V AVDD and 4.0 V DVDD. Always assert RESET (active low) at startup for at least 1 ms before SPI transactions begin.
When interfacing the SPI bus to a host MCU, place a 33 ohm series resistor on each SPI line close to the ADS1299 to dampen ringing from cable or board parasitic capacitance. Keep the SPI traces short (under 50 mm) and route them over a continuous digital ground plane. Use the DRDY signal rather than polling to detect conversion completion; this avoids timing skew between channels when streaming at high data rates.
Compliance Information
RoHS compliant per TI product page. Standard industrial grade; for AEC-Q100 automotive use, the G4 suffix variants (e.g. ADS1299IPAGRG4) provide automotive-grade qualification on the same family.
