ADS1299IPAGR - 8-Ch 24-Bit AFE for EEG/Biopotential | Texas Instruments
MPN： ADS1299IPAGR ✓ 啟用中ADS1299IPAGR 概覽
An analog front end (AFE) is an integrated circuit that combines a low-noise analog signal chain (typically PGA, filters, and ADC reference) with the digitizing converter on a single die. The ADS1299 belongs to the broader hierarchy of mixed-signal data converters, then successive-approximation or delta-sigma ADCs, and finally precision measurement ICs that interface directly with low-amplitude physiological sensors. By integrating the biasing, lead-off detection, and right-leg drive drivers required for EEG/ECG/EMG, the AFE reduces the external component count compared to a discrete ADC-plus-op-amp solution.
Key features include a PGA with gains from 1 to 24 in 7 steps, internal 4.5 V low-drift reference (30 ppm/C typical), internal oscillator, and selectable SPI-compatible serial interface. Input common-mode rejection exceeds 110 dB at 60 Hz, and the integrated bias amplifier supplies patient or subject bias in active electrode circuits. Power consumption is approximately 42 mW per channel with all channels active, while a flexible power-down mode reduces current to microamp levels for wearable battery-powered applications.
Architecturally, the device uses a chopper-stabilized, multi-bit delta-sigma modulator per channel followed by a digital decimation filter. This topology achieves the very low input-referred noise necessary for sub-microvolt biopotential signals while suppressing 1/f and mains interference. The internal reference and oscillator eliminate two critical external components that typically drift across temperature in discrete designs.
Typical applications include electroencephalography (EEG) headsets, polysomnography and sleep monitoring, electrocardiography (ECG/Holter) patient monitors, electromyography (EMG) prosthetics, brain-computer interfaces (BCI), and electrophysiology research instrumentation. In EEG systems the part's CMRR and noise floor allow detection of microvolt-scale cortical signals without complex shielding.
When designing with the ADS1299, place the device on a four-layer PCB with a continuous analog ground plane, route the analog inputs as guarded differential pairs, and use a clean low-noise LDO such as the TPS7A4701 for AVDD to preserve noise performance. Always refer to the manufacturer datasheet and the ADS1299 evaluation module (ADS1299EEGFE-PDK) reference design for layout guidance.
直接替換替代品，適用於 ADS1299IPAGR — 相同封裝，腳位對腳位相容。需重新設計 PCB 的不同封裝零件不列入。
此系列的變體
與下列產品可直接替換的同系列型號： ADS1299IPAGR （相同外形與佔位） — 差異在於 Input-Referred Noise, Internal Reference, Package, Number of Channels, Operating Temperature.
ADS1299IPAG
✅ 直接替換📋 參考替代品（不在目錄中）
ADS1299IPAGRG4
✅ 直接替換 ⚠️ 規格未經驗證📋 參考替代品（不在目錄中）
ADS1299-6PAG
✅ 直接替換聯絡詢價
查看資料表 →ADS1299-4PAG
✅ 直接替換 ⚠️ 規格未經驗證📋 參考替代品（不在目錄中）
ADS1298IPAG
✅ 直接替換聯絡詢價
查看資料表 →ADS1299IPAGR 最大額定值與電氣特性
| Number of Channels | 8 |
| 解析度 | 24 bit |
| Architecture | Delta-Sigma (Delta Sigma) |
| 取樣率 | 16 kSPS per channel (max) |
| PGA Gain Range | 1x to 24x (7 steps) |
| Input-Referred Noise | 0.5 uVpp typical (gain = 24, data rate 250 SPS) |
| Common-Mode Rejection Ratio (CMRR) | 110 dB at 60 Hz |
| Internal Reference | 4.5 V, 30 ppm/C drift |
| Supply Voltage (AVDD) | 5 V (analog supply) |
| Supply Voltage (DVDD) | 1.8 V to 3.6 V (digital supply) |
| Power Dissipation | 42 mW per channel |
| 工作溫度 | -40C to +85C |
| 封裝 | 64-TQFP (PAG) 10x10 mm |
| 介面 | SPI-compatible serial |
| On-chip Features | Bias amplifier, lead-off detection, right-leg drive, internal oscillator |
| 安裝類型 | Surface Mount |
| MSL 等級 | 3 (168 hours) |
| RoHS 狀態 | Compliant |
ADS1299IPAGR 腳位配置
| 腳位 1 | AVDD — Analog supply (5 V typical) |
| 腳位 2 | AVSS — Analog ground |
| 腳位 3 | IN1P — Positive input, channel 1 |
| 腳位 4 | IN1N — Negative input, channel 1 |
| 腳位 5 | DVDD — Digital supply (1.8 V to 3.6 V) |
| 腳位 6 | IN2P — Positive input, channel 2 |
| 腳位 7 | IN2N — Negative input, channel 2 |
| 腳位 8 | IN3P — Positive input, channel 3 |
| 腳位 9 | IN3N — Negative input, channel 3 |
| 腳位 10 | IN4P — Positive input, channel 4 |
| 腳位 11 | IN4N — Negative input, channel 4 |
| 腳位 12 | AVSS — Analog ground |
| 腳位 13 | AVDD1 — Charge-pump analog supply |
| 腳位 14 | VCAP1 — Charge-pump capacitor pin 1 |
| 腳位 15 | VCAP2 — Charge-pump capacitor pin 2 |
| 腳位 16 | AVSS — Analog ground |
| 腳位 17 | AVDD — Analog supply (5 V typical) |
| 腳位 18 | AVSS — Analog ground |
| 腳位 19 | IN5P — Positive input, channel 5 |
| 腳位 20 | IN5N — Negative input, channel 5 |
| 腳位 21 | IN6P — Positive input, channel 6 |
| 腳位 22 | IN6N — Negative input, channel 6 |
| 腳位 23 | IN7P — Positive input, channel 7 |
| 腳位 24 | IN7N — Negative input, channel 7 |
| 腳位 25 | AVSS — Analog ground |
| 腳位 26 | RL — Right-leg drive output |
| 腳位 27 | BIAS — Bias amplifier output |
| 腳位 28 | BIASIN — Bias amplifier input |
| 腳位 29 | AVDD — Analog supply (5 V typical) |
| 腳位 30 | AVSS — Analog ground |
| 腳位 31 | IN8P — Positive input, channel 8 |
| 腳位 32 | IN8N — Negative input, channel 8 |
| 腳位 33 | TESTP — Test signal positive input |
| 腳位 34 | TESTN — Test signal negative input |
| 腳位 35 | AVSS — Analog ground |
| 腳位 36 | VCAP3 — Decoupling capacitor pin 3 |
| 腳位 37 | AVSS — Analog ground |
| 腳位 38 | AVDD — Analog supply (5 V typical) |
| 腳位 39 | AVSS — Analog ground |
| 腳位 40 | VCAP4 — Decoupling capacitor pin 4 |
| 腳位 41 | AVDD — Analog supply (5 V typical) |
| 腳位 42 | AVSS — Analog ground |
| 腳位 43 | GPIO1 — General-purpose IO 1 |
| 腳位 44 | DVDD — Digital supply (1.8 V to 3.6 V) |
| 腳位 45 | DGND — Digital ground |
| 腳位 46 | CLKSEL — Clock select (internal/external) |
| 腳位 47 | PWDN — Power-down input (active low) |
| 腳位 48 | RESET — Reset input (active low) |
| 腳位 49 | CS — SPI chip select (active low) |
| 腳位 50 | SCLK — SPI serial clock |
| 腳位 51 | DIN — SPI serial data input |
| 腳位 52 | DOUT — SPI serial data output |
| 腳位 53 | DRDY — Data ready output (active low) |
| 腳位 54 | GPIO2 — General-purpose IO 2 |
| 腳位 55 | GPIO3 — General-purpose IO 3 |
| 腳位 56 | GPIO4 — General-purpose IO 4 |
| 腳位 57 | DGND — Digital ground |
| 腳位 58 | CLK — External clock input (optional) |
| 腳位 59 | AVSS — Analog ground |
| 腳位 60 | AVDD — Analog supply (5 V typical) |
| 腳位 61 | AVSS — Analog ground |
| 腳位 62 | VCAP5 — Decoupling capacitor pin 5 |
| 腳位 63 | AVSS — Analog ground |
| 腳位 64 | AVDD — Analog supply (5 V typical) |
典型應用
ADS1299IPAGR 適用於 6 應用s: Electroencephalography (EEG) Headsets, Polysomnography and Sleep Monitoring, Electrocardiography (ECG/Holter) Patient Monitors, Brain-Computer Interface (BCI) Hardware, Electromyography (EMG) Prosthetics, Research Electrophysiology Instrumentation.
Electroencephalography (EEG) Headsets
The ADS1299IPAGR is the de facto industry-standard AFE for research-grade EEG headsets and brain-computer interfaces. Its 0.5 uVpp input-referred noise at gain = 24 and 110 dB CMRR at 60 Hz allow detection of sub-microvolt cortical signals without complex shielding, while 8 differential channels natively support 10-20 system montages. The integrated right-leg drive amplifier drives the common-mode voltage back to the subject to actively suppress mains interference, eliminating a discrete op-amp circuit. Placed between Ag/AgCl scalp electrodes and a host MCU, the part's 42 mW per channel power budget stays manageable on lithium-ion powered wireless headsets.
推薦
Polysomnography and Sleep Monitoring
Polysomnography systems combine EEG, EOG, EMG and ECG channels, and the ADS1299IPAGR's 8 differential inputs can serve multiple signal chains from a single device. Its 16 kSPS per channel maximum data rate captures high-frequency neural spikes for sleep-stage scoring, while the internal 4.5 V reference with 30 ppm/C drift keeps the calibration stable across the long recording durations typical of overnight studies. Lead-off detection identifies disconnected electrodes during unattended home sleep tests. Compared to multi-ADC discrete designs, the integrated PGA + ADC + bias amplifier cut board area by roughly 60 percent and simplify regulatory certification.
推薦
Electrocardiography (ECG/Holter) Patient Monitors
Clinical ECG monitors and Holter recorders benefit from the ADS1299IPAGR's high CMRR (110 dB at 60 Hz) to reject mains hum from skin electrodes. With 8 channels the device can monitor multiple chest leads plus limb electrodes from a single chip, simplifying patient-cable management and reducing BOM cost. The internal bias amplifier and right-leg drive circuitry improve signal quality without external op-amps. At 42 mW per channel the device is appropriate for AC-powered bedside monitors and for battery-powered Holter recorders operating from a 3.7 V Li-ion cell through a step-up converter.
推薦
Brain-Computer Interface (BCI) Hardware
Brain-computer interface research platforms rely on the ADS1299IPAGR's combination of high channel count, low noise, and simultaneous sampling to decode neural activity for cursor control, prosthetic command, or research telemetry. Simultaneous sampling eliminates inter-channel skew that would distort evoked-response waveforms, while the 0.5 uVpp noise floor resolves single-unit and multi-unit firing patterns at the scalp. The 64-TQFP (PAG) footprint fits within compact wearable BCI rigs, and the SPI interface streams all 8 channels to an FPGA at data rates up to 128 kSPS aggregate.
推薦
Electromyography (EMG) Prosthetics
Modern myoelectric prosthetic arms decode surface EMG signals from up to 8 forearm muscle sites, which is a perfect fit for the ADS1299IPAGR's 8 differential channels. The integrated PGA with up to 24x gain amplifies the sub-millivolt EMG signals before digitization, eliminating external instrumentation amplifiers. The 16 kSPS per channel rate captures the high-frequency content of muscle contractions needed for proportional motor control. Power dissipation of 42 mW per channel permits battery-powered designs lasting a full day on a small Li-ion cell.
推薦
Research Electrophysiology Instrumentation
University and pharmaceutical electrophysiology rigs use the ADS1299IPAGR as a flexible front end for cell-based assays, microelectrode array recordings, and patch-clamp signal conditioning. The wide PGA gain range (1 to 24) supports both large extracellular spike signals and small field potentials, while the internal 4.5 V reference keeps calibration stable across long multi-hour experiments. SPI connectivity lets researchers pair the part with an FPGA or data-acquisition card for streaming raw waveforms at full 16 kSPS per channel rate without data loss.
推薦
推薦產品摘要
工程參考資料，適用於 ADS1299IPAGR — 比較、設計指引及合規資訊。
選型指南
與替代品比較
| 參數 | 本產品 | ADS1299IPAG | ADS1299IPAGRG4 | ADS1299-6PAG | ADS1299-4PAG | ADS1298IPAG |
|---|---|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | 64-TQFP (PAG) | 64-TQFP (PAG) | 64-TQFP (PAG) | 64-TQFP (PAG) | 64-TQFP (PAG) | 64-TQFP (PAG) |
| Number of Channels | 8 | 8 | 8 | 6 | 4 | 8 |
| Resolution | 24 bit | 24 bit | 24 bit | 24 bit | 24 bit | 24 bit |
| Input-Referred Noise | 0.5 uVpp | 0.5 uVpp | 0.5 uVpp | 0.5 uVpp | 0.5 uVpp | 1.0 uVpp (typical) |
| CMRR @ 60 Hz | 110 dB | 110 dB | 110 dB | 110 dB | 110 dB | 105 dB |
| Max Data Rate | 16 kSPS/ch | 16 kSPS/ch | 16 kSPS/ch | 16 kSPS/ch | 16 kSPS/ch | 32 kSPS/ch |
| PGA Gain Range | 1 to 24 | 1 to 24 | 1 to 24 | 1 to 24 | 1 to 24 | 1 to 12 |
| Operating Temperature | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C |
主要差異化特點
- Lowest input-referred noise in TI's biopotential AFE family (對比ADS1298IPAG)
- Wider PGA gain range than the ADS1298 (對比ADS1298IPAG)
- Pin-compatible family allowing channel-count flexibility (對比ADS1299-6PAG and ADS1299-4PAG)
- Integrated bias amplifier and right-leg drive eliminate external op-amps (對比Discrete ADC + INA + op-amp front end)
設計說明
Power the AVDD rail from an ultra-low-noise LDO such as the Texas Instruments TPS7A4701 (4.17 uVrms, 72 dB PSRR at 1 kHz) rather than a switching converter. A 100 nF X7R bypass placed within 3 mm of each AVDD pin and a 10 uF bulk capacitor on the AVSS side reduces switching noise coupling. DVDD may be derived from any low-noise 1.8 V to 3.6 V LDO; the part tolerates separate analog and digital supplies for isolation.
Use a four-layer PCB with a continuous uninterrupted analog ground plane on layer 2 below the IC; avoid routing digital signals across the analog ground island. Route each differential input pair (INxP, INxN) as a tightly coupled guarded pair with characteristic impedance of 50 ohms. Keep the right-leg drive (RL) and bias (BIAS) traces short and surrounded by ground pours to prevent parasitic capacitance from destabilizing the loop. Refer to TI's ADS1299EEGFE-PDK reference design for the recommended layout.
Do not leave VCAP1 through VCAP5 floating; each requires a 1 uF X7R capacitor to AVSS to stabilize the internal charge pump. Failing to populate these caps will result in unstable internal rails and degraded CMRR. Also, do not exceed 5.5 V on AVDD or 3.6 V on DVDD; the absolute maximum ratings per the datasheet are 6.0 V AVDD and 4.0 V DVDD. Always assert RESET (active low) at startup for at least 1 ms before SPI transactions begin.
When interfacing the SPI bus to a host MCU, place a 33 ohm series resistor on each SPI line close to the ADS1299 to dampen ringing from cable or board parasitic capacitance. Keep the SPI traces short (under 50 mm) and route them over a continuous digital ground plane. Use the DRDY signal rather than polling to detect conversion completion; this avoids timing skew between channels when streaming at high data rates.
合規資訊
RoHS compliant per TI product page. Standard industrial grade; for AEC-Q100 automotive use, the G4 suffix variants (e.g. ADS1299IPAGRG4) provide automotive-grade qualification on the same family.
