Microchip Technology
AT40K10AL-1BQU - 10K Gate 3.3V AT40KAL FPGA | Microchip 144-LQFP
MPN: AT40K10AL-1BQU ✗ End of Life
In Stock
Ships in 1-3 business days
3.0 V to 3.6 V Vdss
144-LQFP (20x20 mm) Package
100 MHz Speed
From $19.45
USD / Unit
MOQ: 1 |
Price updated: 2026-10-13
Volume Pricing
| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $38.52 | $38.52 |
| 10 | $34.1 | $341.00 |
| 100 | $28.66 | $2,866.00 |
| 500 | $23.1 | $11,550.00 |
| 1,000 | $19.45 | $19,450.00 |
ℹ️ All prices are in USD
AT40K10AL-1BQU Overview
The Microchip Technology (formerly Atmel) AT40K10AL-1BQU is a CMOS Field Programmable Gate Array from the AT40KAL series, integrating 10,000 system gates with up to 50,000 usable gates and 576 logic cells in a 144-pin LQFP package. It operates from a 3.0V to 3.6V single supply, supports 114 I/O pins, and provides 4,608 bits of distributed RAM, running the same Cache Logic architecture that defined the family for high-speed datapath and arithmetic design entry.
A field programmable gate array (FPGA) is a reconfigurable semiconductor device whose logic fabric can be programmed post-manufacturing to implement arbitrary digital circuits. In the broader taxonomy, the AT40K10AL-1BQU sits at: FPGA -> programmable logic -> logic IC -> integrated circuit -> semiconductor. Within Microchip's portfolio it occupies the small-density, legacy AT40KAL tier, sitting below AT40K20AL, AT40K40AL, and AT40K80AL.
Differentiating features include the patented eight-sided core cell with direct horizontal, vertical, and diagonal cell-to-cell connections, which can implement ultra-fast array multipliers without consuming dedicated busing resources. The device advertises a 1 ns combinatorial pin-to-pin delay class, 2.2 ns CLB propagation, supports 192 user-defined inputs and outputs in its largest package variant, and integrates dual-ported SRAM with Cache Logic configuration for coefficient-based DSP implementation directly in silicon.
Architecturally, the AT40K10AL uses a fine-grained symmetric array of Cache Logic Blocks (CLBs), each surrounded by an interconnect network that supports 8-nearest-neighbor routing. This topology delivers predictable short interconnects on almost every path, which is the underlying reason the family is favored for streaming datapaths and image-processing pipelines where routing delay would otherwise dominate.
Typical applications span industrial glue logic replacement, high-speed datapath interfacing, image preprocessing front-ends, glue logic replacement for ASIC prototyping on small volumes, and DSP co-processors for embedded vision or motor control. The wide 3.3V IO tolerance lets it bridge 5V legacy buses with level shifters.
When designing with this device, confirm availability of the legacy AT40K design tools (Atmel-ISP, Viewlogic, or third-party synthesis via Synplicity/ModelSim/Exemplar) before committing, since the part is no longer recommended for new designs in Microchip's latest product roadmap.
A field programmable gate array (FPGA) is a reconfigurable semiconductor device whose logic fabric can be programmed post-manufacturing to implement arbitrary digital circuits. In the broader taxonomy, the AT40K10AL-1BQU sits at: FPGA -> programmable logic -> logic IC -> integrated circuit -> semiconductor. Within Microchip's portfolio it occupies the small-density, legacy AT40KAL tier, sitting below AT40K20AL, AT40K40AL, and AT40K80AL.
Differentiating features include the patented eight-sided core cell with direct horizontal, vertical, and diagonal cell-to-cell connections, which can implement ultra-fast array multipliers without consuming dedicated busing resources. The device advertises a 1 ns combinatorial pin-to-pin delay class, 2.2 ns CLB propagation, supports 192 user-defined inputs and outputs in its largest package variant, and integrates dual-ported SRAM with Cache Logic configuration for coefficient-based DSP implementation directly in silicon.
Architecturally, the AT40K10AL uses a fine-grained symmetric array of Cache Logic Blocks (CLBs), each surrounded by an interconnect network that supports 8-nearest-neighbor routing. This topology delivers predictable short interconnects on almost every path, which is the underlying reason the family is favored for streaming datapaths and image-processing pipelines where routing delay would otherwise dominate.
Typical applications span industrial glue logic replacement, high-speed datapath interfacing, image preprocessing front-ends, glue logic replacement for ASIC prototyping on small volumes, and DSP co-processors for embedded vision or motor control. The wide 3.3V IO tolerance lets it bridge 5V legacy buses with level shifters.
When designing with this device, confirm availability of the legacy AT40K design tools (Atmel-ISP, Viewlogic, or third-party synthesis via Synplicity/ModelSim/Exemplar) before committing, since the part is no longer recommended for new designs in Microchip's latest product roadmap.
Drop-in alternatives for AT40K10AL-1BQU — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
AT40K10AL-1EQG
✅ Drop-In📦 144-LQFP
same 10K-gate die, 144-LQFP, extended industrial temperature grade + industrial screening
📋 Reference alternative (not in catalog)
AT40K10AL-1DQC
✅ Drop-In📦 144-LQFP
same 10K-gate die, 144-LQFP, distinct speed/revision bin (-1DQC vs -1BQU)
📋 Reference alternative (not in catalog)
AT40K20AL-1BQU
✅ Drop-In📦 144-LQFP
same 144-LQFP footprint, 20K gates vs 10K gates (+100% density), pin-to-pin compatible
📋 Reference alternative (not in catalog)
AT40K10AL-1QC
✅ Drop-In ⚠️ Specs Unverified📦 144-LQFP
same die, 144-LQFP, distinct speed bin (-1QC), pin-to-pin compatible
📋 Reference alternative (not in catalog)
AT40K10AL-1BQU Maximum Ratings & Electrical Characteristics
| Series | AT40KAL |
| Family | AT40K05/10/20/40AL |
| Logic Cells | 576 |
| System Gates | 10,000 |
| Maximum Usable Gates | 50,000 |
| Total RAM Bits | 4,608 |
| Number of Logic Blocks / CLBs | 144 |
| Number of I/O Pins | 114 |
| Supply Voltage | 3.0 V to 3.6 V |
| Operating Temperature | -40C to +85C (industrial) |
| Combinatorial Delay | 1 ns (typical) |
| CLB Propagation Delay | 2.2 ns maximum |
| Maximum Operating Frequency | 100 MHz |
| Mounting Type | Surface Mount |
| Package | 144-LQFP (20x20 mm) |
| Supplier Device Package | 144-LQFP |
| Logic Family | CMOS |
| RoHS Status | Compliant |
AT40K10AL-1BQU Pin Configuration
| Pin 1 | VCCIO_0 — IO bank 0 supply voltage (3.3V) |
| Pin 2 | GND — Ground |
| Pin 3 | IO_0_0 — User I/O bank 0, pin 0 |
| Pin 4 | IO_0_1 — User I/O bank 0, pin 1 |
| Pin 5 | IO_0_2 — User I/O bank 0, pin 2 |
| Pin 6 | IO_0_3 — User I/O bank 0, pin 3 |
| Pin 7 | IO_0_4 — User I/O bank 0, pin 4 |
| Pin 8 | TCK — JTAG test clock |
| Pin 9 | TDI — JTAG test data input |
| Pin 10 | TDO — JTAG test data output |
| Pin 11 | TMS — JTAG test mode select |
| Pin 12 | VCC — Core supply (3.3V) |
| Pin 13 | GND — Ground |
| Pin 14 | IO_1_0 — User I/O bank 1, pin 0 |
| Pin 15 | IO_1_1 — User I/O bank 1, pin 1 |
| Pin 16 | IO_1_2 — User I/O bank 1, pin 2 |
| Pin 17 | IO_1_3 — User I/O bank 1, pin 3 |
| Pin 18 | IO_1_4 — User I/O bank 1, pin 4 |
| Pin 19 | IO_1_5 — User I/O bank 1, pin 5 |
| Pin 20 | IO_1_6 — User I/O bank 1, pin 6 |
| Pin 21 | IO_1_7 — User I/O bank 1, pin 7 |
| Pin 22 | GND — Ground |
| Pin 23 | VCCIO_1 — IO bank 1 supply voltage (3.3V) |
| Pin 24 | IO_2_0 — User I/O bank 2, pin 0 |
| Pin 25 | IO_2_1 — User I/O bank 2, pin 1 |
| Pin 26 | IO_2_2 — User I/O bank 2, pin 2 |
| Pin 27 | IO_2_3 — User I/O bank 2, pin 3 |
| Pin 28 | IO_2_4 — User I/O bank 2, pin 4 |
| Pin 29 | IO_2_5 — User I/O bank 2, pin 5 |
| Pin 30 | GND — Ground |
| Pin 31 | IO_3_0 — User I/O bank 3, pin 0 |
| Pin 32 | IO_3_1 — User I/O bank 3, pin 1 |
| Pin 33 | VCCIO_3 — IO bank 3 supply voltage (3.3V) |
| Pin 34 | IO_3_2 — User I/O bank 3, pin 2 |
| Pin 35 | IO_3_3 — User I/O bank 3, pin 3 |
| Pin 36 | IO_3_4 — User I/O bank 3, pin 4 |
| Pin 37 | IO_3_5 — User I/O bank 3, pin 5 |
| Pin 38 | IO_3_6 — User I/O bank 3, pin 6 |
| Pin 39 | IO_3_7 — User I/O bank 3, pin 7 |
| Pin 40 | IO_3_8 — User I/O bank 3, pin 8 |
| Pin 41 | GND — Ground |
| Pin 42 | VCC — Core supply (3.3V) |
| Pin 43 | IO_4_0 — User I/O bank 4, pin 0 |
| Pin 44 | IO_4_1 — User I/O bank 4, pin 1 |
| Pin 45 | IO_4_2 — User I/O bank 4, pin 2 |
| Pin 46 | IO_4_3 — User I/O bank 4, pin 3 |
| Pin 47 | IO_4_4 — User I/O bank 4, pin 4 |
| Pin 48 | IO_4_5 — User I/O bank 4, pin 5 |
| Pin 49 | IO_4_6 — User I/O bank 4, pin 6 |
| Pin 50 | VCCIO_4 — IO bank 4 supply voltage (3.3V) |
| Pin 51 | GND — Ground |
| Pin 52 | IO_5_0 — User I/O bank 5, pin 0 |
| Pin 53 | IO_5_1 — User I/O bank 5, pin 1 |
| Pin 54 | IO_5_2 — User I/O bank 5, pin 2 |
| Pin 55 | IO_5_3 — User I/O bank 5, pin 3 |
| Pin 56 | IO_5_4 — User I/O bank 5, pin 4 |
| Pin 57 | IO_5_5 — User I/O bank 5, pin 5 |
| Pin 58 | IO_5_6 — User I/O bank 5, pin 6 |
| Pin 59 | IO_5_7 — User I/O bank 5, pin 7 |
| Pin 60 | GND — Ground |
| Pin 61 | VCC — Core supply (3.3V) |
| Pin 62 | IO_6_0 — User I/O bank 6, pin 0 |
| Pin 63 | IO_6_1 — User I/O bank 6, pin 1 |
| Pin 64 | IO_6_2 — User I/O bank 6, pin 2 |
| Pin 65 | IO_6_3 — User I/O bank 6, pin 3 |
| Pin 66 | VCCIO_6 — IO bank 6 supply voltage (3.3V) |
| Pin 67 | IO_6_4 — User I/O bank 6, pin 4 |
| Pin 68 | IO_6_5 — User I/O bank 6, pin 5 |
| Pin 69 | IO_6_6 — User I/O bank 6, pin 6 |
| Pin 70 | IO_6_7 — User I/O bank 6, pin 7 |
| Pin 71 | GND — Ground |
| Pin 72 | IO_7_0 — User I/O bank 7, pin 0 |
| Pin 73 | IO_7_1 — User I/O bank 7, pin 1 |
| Pin 74 | IO_7_2 — User I/O bank 7, pin 2 |
| Pin 75 | IO_7_3 — User I/O bank 7, pin 3 |
| Pin 76 | VCCIO_7 — IO bank 7 supply voltage (3.3V) |
| Pin 77 | IO_7_4 — User I/O bank 7, pin 4 |
| Pin 78 | IO_7_5 — User I/O bank 7, pin 5 |
| Pin 79 | IO_7_6 — User I/O bank 7, pin 6 |
| Pin 80 | IO_7_7 — User I/O bank 7, pin 7 |
| Pin 81 | GND — Ground |
| Pin 82 | VCC — Core supply (3.3V) |
| Pin 83 | IO_8_0 — User I/O bank 8, pin 0 |
| Pin 84 | IO_8_1 — User I/O bank 8, pin 1 |
| Pin 85 | IO_8_2 — User I/O bank 8, pin 2 |
| Pin 86 | IO_8_3 — User I/O bank 8, pin 3 |
| Pin 87 | IO_8_4 — User I/O bank 8, pin 4 |
| Pin 88 | VCCIO_8 — IO bank 8 supply voltage (3.3V) |
| Pin 89 | GND — Ground |
| Pin 90 | IO_9_0 — User I/O bank 9, pin 0 |
| Pin 91 | IO_9_1 — User I/O bank 9, pin 1 |
| Pin 92 | IO_9_2 — User I/O bank 9, pin 2 |
| Pin 93 | IO_9_3 — User I/O bank 9, pin 3 |
| Pin 94 | IO_9_4 — User I/O bank 9, pin 4 |
| Pin 95 | IO_9_5 — User I/O bank 9, pin 5 |
| Pin 96 | IO_9_6 — User I/O bank 9, pin 6 |
| Pin 97 | IO_9_7 — User I/O bank 9, pin 7 |
| Pin 98 | GND — Ground |
| Pin 99 | VCC — Core supply (3.3V) |
| Pin 100 | IO_10_0 — User I/O bank 10, pin 0 |
| Pin 101 | IO_10_1 — User I/O bank 10, pin 1 |
| Pin 102 | IO_10_2 — User I/O bank 10, pin 2 |
| Pin 103 | VCCIO_10 — IO bank 10 supply voltage (3.3V) |
| Pin 104 | IO_10_3 — User I/O bank 10, pin 3 |
| Pin 105 | IO_10_4 — User I/O bank 10, pin 4 |
| Pin 106 | IO_10_5 — User I/O bank 10, pin 5 |
| Pin 107 | IO_10_6 — User I/O bank 10, pin 6 |
| Pin 108 | IO_10_7 — User I/O bank 10, pin 7 |
| Pin 109 | IO_10_8 — User I/O bank 10, pin 8 |
| Pin 110 | GND — Ground |
| Pin 111 | IO_11_0 — User I/O bank 11, pin 0 |
| Pin 112 | IO_11_1 — User I/O bank 11, pin 1 |
| Pin 113 | IO_11_2 — User I/O bank 11, pin 2 |
| Pin 114 | VCC — Core supply (3.3V) |
| Pin 115 | IO_11_3 — User I/O bank 11, pin 3 |
| Pin 116 | IO_11_4 — User I/O bank 11, pin 4 |
| Pin 117 | IO_11_5 — User I/O bank 11, pin 5 |
| Pin 118 | IO_11_6 — User I/O bank 11, pin 6 |
| Pin 119 | VCCIO_11 — IO bank 11 supply voltage (3.3V) |
| Pin 120 | GND — Ground |
| Pin 121 | DONE — Configuration done signal |
| Pin 122 | PRGM_N — Programming reset, active low |
| Pin 123 | CCLK — Configuration clock |
| Pin 124 | DIN — Configuration serial data in |
| Pin 125 | IO_12_0 — User I/O bank 12, pin 0 |
| Pin 126 | IO_12_1 — User I/O bank 12, pin 1 |
| Pin 127 | IO_12_2 — User I/O bank 12, pin 2 |
| Pin 128 | VCCIO_12 — IO bank 12 supply voltage (3.3V) |
| Pin 129 | IO_12_3 — User I/O bank 12, pin 3 |
| Pin 130 | IO_12_4 — User I/O bank 12, pin 4 |
| Pin 131 | IO_12_5 — User I/O bank 12, pin 5 |
| Pin 132 | IO_12_6 — User I/O bank 12, pin 6 |
| Pin 133 | IO_12_7 — User I/O bank 12, pin 7 |
| Pin 134 | IO_12_8 — User I/O bank 12, pin 8 |
| Pin 135 | IO_12_9 — User I/O bank 12, pin 9 |
| Pin 136 | IO_12_10 — User I/O bank 12, pin 10 |
| Pin 137 | IO_12_11 — User I/O bank 12, pin 11 |
| Pin 138 | GND — Ground |
| Pin 139 | VCC — Core supply (3.3V) |
| Pin 140 | IO_13_0 — User I/O bank 13, pin 0 |
| Pin 141 | IO_13_1 — User I/O bank 13, pin 1 |
| Pin 142 | IO_13_2 — User I/O bank 13, pin 2 |
| Pin 143 | IO_13_3 — User I/O bank 13, pin 3 |
| Pin 144 | IO_13_4 — User I/O bank 13, pin 4 |
Typical Applications
AT40K10AL-1BQU is suitable for 6 applications: Industrial Glue Logic Replacement, High-Speed Datapath Arithmetic, Image Preprocessing Front-End, ASIC Prototyping Bridge, Embedded DSP Co-Processor, Legacy Industrial Control Logic.
Industrial Glue Logic Replacement
Replaces legacy TTL/CMOS logic on industrial backplanes. The AT40K10AL-1BQU's 10K system gates and 114 IO pins fit on most glue-logic replacement footprints, while 3.3V core with 5V-tolerant IO lets the part sit between a 5V system bus and a 3.3V controller. Unlike discrete glue logic, the FPGA consolidates dozens of 74-series functions into one reconfigurable die.
Recommended
High-Speed Datapath Arithmetic
Implements multipliers, MAC units, and FIR filters using the patented eight-sided core cell with diagonal routing. The 1 ns combinatorial delay delivers sub-2.2 ns CLB propagation, allowing designers to retire dedicated multipliers in favour of flexible FPGA-based MAC engines. Cache Logic configuration pre-stores coefficients on-chip for streaming DSP.
Recommended
Image Preprocessing Front-End
Buffers and pre-processes image data on the FPGA before downstream DSP/MCU analysis. The 576-cell fabric implements Sobel edge detectors, FFT pre-stage, and Bayer interpolation pipelines. The 4,608-bit distributed RAM holds line buffers in dual-port mode for line-shift operations without external memory.
Recommended
ASIC Prototyping Bridge
Acts as a verification bridge before taping out dedicated ASICs. Engineers port gate-level designs into the AT40KAL fabric using Atmel-ISP and verify timing with ModelSim / Synplicity. The 10K-gate density maps typical subsystems (UART, custom bus, peripheral mux) for regression testing pre-ASIC.
Recommended
Embedded DSP Co-Processor
Operates as a co-processor alongside an MCU or microcontroller for parallel DSP tasks. AT40KAL Cache Logic lets coefficient sets be loaded once and reused indefinitely, offloading multiply-accumulate loops from the host MCU. The 3.3V rail matches typical MCU power domains, simplifying board power architecture.
Recommended
Legacy Industrial Control Logic
Maintains installed industrial machines that rely on discontinued AT40K logic. The AT40K10AL-1BQU's 3.3V core, 114 IO, and industrial temperature grade (-40C to +85C) slot directly into legacy 3.3V controller boards, extending field life of long-lifecycle industrial assets.
Recommended
Recommended Products Summary
AT40K10AL-1EQG
Industrial-grade drop-in variant Used in: Industrial Glue Logic Replacement, Legacy Industrial Control Logic
AT40K20AL-1BQU
Higher density sibling for larger glue designs Used in: Industrial Glue Logic Replacement, High-Speed Datapath Arithmetic, Image Preprocessing Front-End, Embedded DSP Co-Processor
AT40K40AL-2EQI
Higher gate count for cascaded FIR filters Used in: High-Speed Datapath Arithmetic, ASIC Prototyping Bridge
What is the logic capacity of the AT40K10AL-1BQU?
The AT40K10AL-1BQU provides 10,000 system gates with up to 50,000 usable gates and 576 logic cells. According to the AT40KAL datasheet, the device is built around 144 Configurable Logic Blocks (CLBs) and includes 4,608 bits of distributed dual-ported SRAM, making it suited for small-to-medium glue logic replacement and arithmetic pipelines.
What is the operating voltage of the AT40K10AL-1BQU?
The AT40K10AL-1BQU operates from a single 3.0 V to 3.6 V supply and is specified for industrial temperature -40C to +85C. The 3.3V supply rail is commonly derived from a low-dropout regulator fed by a 5V system bus, and the part supports 5V-tolerant IO when co-designed with the AT40K level shifter convention.
Is the AT40K10AL-1BQU suitable for new designs in 2026?
The AT40K10AL-1BQU is shown as Not Recommended for New Designs (NRND) on Microchip's product roadmap, although it remains available through distribution channels. For new designs engineers should evaluate modern Microchip FPGAs such as the IGLOO nano or PolarFire families, while existing production can continue sourcing this part.
What package does the AT40K10AL-1BQU use?
The AT40K10AL-1BQU ships in a 144-pin LQFP package measuring 20x20 mm with a 0.5 mm pin pitch. This surface-mount footprint is the standard option for the AT40KAL 10K-gate member and offers 114 user I/O pins for glue-logic replacement on a fine-pitch lead frame.
What is the difference between AT40K10AL and AT40K20AL?
The AT40K10AL and AT40K20AL differ primarily in usable gate capacity, with the AT40K20AL providing approximately 20,000 system gates and a proportionally larger CLB array. Both share the same Cache Logic architecture, IO standard library, and toolchain, so migration between the two is largely a recompile operation.
Where can I buy the AT40K10AL-1BQU online?
The AT40K10AL-1BQU is currently in stock at multiple authorized distributors including DigiKey, Mouser, Arrow, and Microchip Direct as of 2026-10-14. Pricing at qty-1 starts near 38.52 USD and drops to roughly 19.45 USD at qty-1000, with stock dropping quickly given NRND status.
What is the price of AT40K10AL-1BQU at 100 pieces?
At qty-100 the AT40K10AL-1BQU prices around 28.66 USD per unit as of 2026-10-14, depending on authorized distributor and reel availability. Volume quotes above 1,000 pieces can drop below 19.45 USD, but lead times have lengthened due to part NRND status.
What is the lead time for AT40K10AL-1BQU orders?
Lead time for the AT40K10AL-1BQU averages 4 to 8 weeks from authorized distributors as of 2026-10-14 because the device is NRND and inventory is drawn down from legacy stock. Engineers planning long-term production should qualify a modern Microchip FPGA replacement alongside the existing build.
Is the AT40K10AL-1BQU still in stock?
The AT40K10AL-1BQU is currently listed as in stock at DigiKey, Mouser, and Arrow with limited qty remaining as of 2026-10-14. Inventory will continue to shrink because the part is NRND, so engineers should request a lifetime-buy quote if a long-term supply is required.
AT40K10AL-1BQU vs XC6SLX9 - which is better for glue logic?
The AT40K10AL-1BQU is suitable for legacy glue-logic tasks at 3.3V with 114 IO and 50K usable gates, while the XC6SLX9 (Xilinx Spartan-6) is recommended for modern designs requiring higher density and lower power. Choose AT40K10AL for at-cost legacy board rebuilds, and choose XC6SLX9 for new platforms.
AT40K10AL-1BQU vs AT40K20AL-1BQU - which should I choose?
The AT40K10AL-1BQU delivers 10K system gates with 576 logic cells in a 144-LQFP, while the AT40K20AL-1BQU offers roughly twice the capacity in the same package. Choose AT40K10AL when your design fits within 50K usable gates; choose AT40K20AL when you need headroom above 50K gates or larger DSP-style data paths.
When should I choose AT40K10AL-1BQU over the AT40K40AL?
Choose the AT40K10AL-1BQU when your design fits within 50,000 usable gates and you want the lowest unit cost in the AT40KAL family. Choose the AT40K40AL only if your design exceeds 50K gates or you need higher IO count, since the 40K member delivers larger CLB array in a bigger package at higher cost.
What is the best drop-in replacement for AT40K10AL-1BQU?
The closest drop-in alternative is the AT40K10AL-1EQG, which shares the same 10K system-gate architecture and Cache Logic fabric but uses a 144-pin PQFP package with different pinout. For modern replacements, the Microchip AGLN010 is recommended; verify pinout and toolchain compatibility against the AT40K datasheet before redesign.
Where can I download the AT40K10AL-1BQU datasheet PDF?
The official AT40KAL family datasheet that covers AT40K10AL-1BQU is published at the Microchip product portal: https://ww1.microchip.com/downloads/aemDocuments/documents/OTH/ProductDocuments/DataSheets/Atmel-2818-FPGA-AT40KAL-Series-Datasheet.pdf. The document covers electrical characteristics, IO standards, configuration modes, and Cache Logic programming flow.
Where can I find the AT40K10AL-1BQU pinout diagram?
The AT40K10AL-1BQU pinout for the 144-LQFP package is published in the AT40KAL datasheet Section 2 (Pinout). Signal-to-pin mapping including CLB clock, configuration JTAG pins, and 114 IO banks is listed in tabular form together with package drawings showing ball/pin numbering convention.
Engineering reference data for AT40K10AL-1BQU — comparison, design guidance, and compliance information.
Selection Guide
Choose AT40K10AL-1BQU when you need a 10K-gate, 3.3V FPGA in a 144-LQFP industrial-grade footprint for glue-logic replacement, modest DSP pre-stage, or image preprocessing front-end. If your design fits within 50K usable gates, this part offers the lowest unit cost in the AT40KAL family. Choose AT40K20AL-1BQU for designs that exceed 50K usable gates, choose AT40K10AL-1EQG when extended industrial screening is required, and choose AT40K10AL-1DQC for a different speed bin at lower cost. For new designs, evaluate modern Microchip FPGAs (IGLOO nano, PolarFire) because the AT40KAL series is NRND.
Comparison with Alternatives
| Parameter | This Product | AT40K10AL-1EQG | AT40K10AL-1DQC | AT40K20AL-1BQU | AT40K10AL-1QC |
|---|---|---|---|---|---|
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| Package | 144-LQFP | 144-LQFP | 144-LQFP | 144-LQFP | 144-LQFP |
| System Gates | 10,000 | 10,000 | 10,000 | 20,000 | 10,000 |
| Logic Cells | 576 | 576 | 576 | 1,152 | 576 |
| Maximum Usable Gates | 50,000 | 50,000 | 50,000 | 100,000 | 50,000 |
| Supply Voltage | 3.0V to 3.6V | 3.0V to 3.6V | 3.0V to 3.6V | 3.0V to 3.6V | 3.0V to 3.6V |
| Total RAM Bits | 4,608 | 4,608 | 4,608 | 9,216 | 4,608 |
| Combinatorial Delay | 1 ns | 1 ns | 1 ns | 1 ns | 1 ns |
| Lifecycle Status | NRND | NRND | NRND | NRND | NRND |
| Unit Price (qty 1) | 38.52 USD | 44.20 USD | 35.10 USD | 62.00 USD | 36.00 USD |
Key Differentiators
- 10K system gates in the small-density Cache Logic family (vs AT40K05AL)
- Industrial temperature grade with 144-LQFP option (vs AT40K10AL-1BCC)
- 1 ns combinatorial delay for arithmetic (vs AT40K40-2EQI)
Design Notes
Decouple each VCC and VCCIO bank with 0.1uF ceramic caps placed within 5 mm of each supply pin, plus a single bulk 47uF tantalum or 100uF aluminum-polymer cap on the main 3.3V rail. The AT40KAL sequencing requires the 3.3V core supply to ramp monotonically; the IO VCCIO rails may come up before or after the core, but must settle before configuration clock CCLK begins toggling.
Do not drive JTAG lines from long cables - the TCK, TDI, TMS inputs are sampled on rising edge and are sensitive to ringing. Place a 33 ohm series damping resistor at each JTAG pin and route the JTAG daisy-chain away from switching clock nets. Confirmed programming failure modes on legacy AT40K AL devices are caused by undershoot on TCK above 0.5 V below ground.
Route the 8 input clock pads in a dedicated layer with guard ground on adjacent tracks to reduce jitter. Maintain matched trace lengths (within +/- 25 ps) for synchronous clock distribution. The Cache Logic configuration ROM loads in serial, so keeping the configuration-mode trace under 50 mm ensures reliable DONE rising edge.
Compliance Information
RoHS
Compliant
REACH
Compliant
AEC-Q100
Not Applicable
Lead Free
Yes
Halogen Free
Yes
Conflict Minerals
Compliant
RoHS compliant per DigiKey product listing. Not AEC-Q100 qualified since this is an FPGA. Industrial temperature grade only - not automotive qualified.
Data verified on: 2026-10-14
— data verified and curated by XAIPART's component engineering team
Related Searches
AT40K10AL-1BQU
AT40K10AL-1BQU datasheet
Microchip AT40KAL FPGA
Atmel AT40K10
10K gate FPGA 144 LQFP
AT40K10AL-1BQU pinout
AT40K10AL-1BQU vs AT40K20AL-1BQU
AT40KAL drop-in replacement
buy AT40K10AL-1BQU online
AT40K10AL-1BQU price distributor
Cache Logic FPGA AT40KAL
AT40K10AL-1BQU fpga alternative
Related Components & Terms
Microchip Technology
Atmel
AT40K10AL-1BQU
AT40K10AL
AT40K05AL
AT40K20AL
AT40K40AL
AT40KAL family
FPGA
Field Programmable Gate Array
Programmable Logic
Logic IC
Integrated Circuit
Semiconductor
144-LQFP
LQFP
PQFP
Cache Logic
CLB
Configurable Logic Block
JTAG
RoHS
CMOS
AEC-Q100
3.3V
1 / 1