CD4017BK - 10-Output CMOS Decade Counter | Texas Instruments
MPN: CD4017BK ✓ ActiveCD4017BK Overview
A decade counter is a synchronous sequential digital circuit that advances through ten states before repeating. The CD4017B family belongs to the CMOS 4000-series logic hierarchy, combining decade counter, counter/divider, and decoded-output functions in one integrated circuit. Its ten mutually exclusive outputs make it useful for implementing cyclic step sequences, frequency division, programmable timing, and sequential control without requiring a separate output decoder.
The key operating features include a supply-voltage range of 3 V to 18 V, a nominal 5 V operating point, and a maximum clock frequency of 11 MHz. The listed propagation delay is 650 ns, while the minimum maximum-frequency figure is 5.5 MHz. The clock input uses Schmitt-trigger action, which improves noise immunity and permits slower clock edges than a conventional logic input. A clock-inhibit input provides a second means of controlling count progression, and the reset input returns the internal count to the zero state.
Internally, the CD4017B is a five-stage Johnson counter followed by decoding circuitry that produces ten individual outputs. Only one decoded output is active for a given count state, allowing the outputs to control a sequence of ten steps. The clock-inhibit and reset functions give the circuit useful control behavior for counters, dividers, stepper-motor sequencers, and cyclic controllers, while the Schmitt-trigger clock input helps prevent false counting on slow or noisy transitions.
Typical applications include decade frequency dividers, ten-step relay or lamp sequences, timing generators, industrial step sequencing, pulse-position indicators, and embedded control systems that require one-hot decoded states. In a divide-by-ten arrangement, the tenth decoded output can feed the clock input to produce an integer division of the input frequency. In a sequencer, the ten outputs can be connected to relays, lamps, or discrete control stages to create repeating operating steps.
The principal design consideration is the relationship between clock frequency, supply voltage, and propagation delay. Timing calculations should include the 650 ns propagation-delay figure and the specified operating-frequency limits instead of assuming ideal zero-delay transitions. The reset and clock-inhibit inputs should be driven with clean logic levels, and unused inputs must remain in a defined state to prevent unintended count advancement.
This page combines the device function, electrical limits, pin assignments, practical application guidance, and verified manufacturer links. It also distinguishes the CFP-16 CD4017BK from CD4017B versions offered in other package technologies, helping engineers confirm footprint and qualification requirements before beginning a PCB or replacement design.
Drop-in alternatives for CD4017BK — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
No drop-in alternatives available for this product.
Request AlternativesCD4017BK Maximum Ratings & Electrical Characteristics
| Counter Type | Decade counter with 10 decoded outputs |
| Logic Family | CMOS 4000 series |
| Supply Voltage Range | 3 V to 18 V |
| Nominal Supply Voltage | 5 V |
| Maximum Clock Frequency | 11 MHz |
| Minimum Maximum-Frequency Figure | 5.5 MHz |
| Propagation Delay | 650 ns |
| Decoded Output Count | 10 outputs |
| Counter Bit Count | 10 bit |
| Clock Triggering | Rising edge |
| Counter Element Count | 1 element |
| Logic Polarity | Positive, negative |
| Maximum Operating Temperature | 125 °C |
| Package | 16-lead CFP-16 ceramic flat package |
| Mounting Type | Through-hole ceramic flat package |
| Input Count | 3 inputs: clock, clock inhibit, and reset |
CD4017BK Pin Configuration
| Pin 1 | CLK — Clock input |
| Pin 2 | CLK INH — Clock inhibit input |
| Pin 3 | RESET — Reset input |
| Pin 4 | Q0 — Decoded output for count state 0 |
| Pin 5 | Q1 — Decoded output for count state 1 |
| Pin 6 | Q2 — Decoded output for count state 2 |
| Pin 7 | Q3 — Decoded output for count state 3 |
| Pin 8 | Q4 — Decoded output for count state 4 |
| Pin 9 | Q5 — Decoded output for count state 5 |
| Pin 10 | Q6 — Decoded output for count state 6 |
| Pin 11 | Q7 — Decoded output for count state 7 |
| Pin 12 | Q8 — Decoded output for count state 8 |
| Pin 13 | Q9 — Decoded output for count state 9 |
| Pin 14 | VSS — Ground reference |
| Pin 15 | VDD — Positive supply voltage |
| Pin 16 | CARRY OUT — Carry output |
Typical Applications
CD4017BK is suitable for 6 applications: Decade Frequency Divider, Ten-Step Relay Sequencer, Industrial Timing and Control, Cyclic Lamp Chase, Pulse and Timing Signal Generation, Counter and Divider Module.
Decade Frequency Divider
The CD4017BK is suitable for dividing an input clock by ten because its ten decoded outputs follow the ten states of a decade counter. A designer can connect Q9 back to the clock input to obtain one output cycle for each ten input-clock cycles. The 3 V to 18 V supply range supports multiple logic environments, while the Schmitt-trigger clock input improves behavior with slow or noisy timing waveforms. Timing analysis should include the listed 650 ns propagation delay and the 11 MHz maximum clock frequency. The circuit is particularly useful when integer decade division is needed without a programmable timer or microcontroller.
Recommended
Ten-Step Relay Sequencer
The CD4017BK can drive a repeating ten-step sequence because one of Q0 through Q9 is active for each count state. Each decoded output may control a relay, indicator, or logic stage, creating cyclic equipment operation from a single clock source. The reset input establishes a repeatable starting state, while clock inhibit can pause the sequence without losing the current step. Because each relay driver may require isolation or additional current amplification, check output-drive limits in the Texas Instruments datasheet. The ceramic CFP-16 package may also suit applications where long-term thermal stability and through-hole construction are priorities.
Recommended
Industrial Timing and Control
The CD4017BK fits fixed-duration industrial timing and control blocks because it combines ten decoded states with clock, inhibit, and reset inputs. It can initiate different machine stages, select timing taps, or trigger discrete control logic without occupying a microcontroller port. The nominal 5 V operating point is compatible with conventional 5 V CMOS systems, and the documented 3 V to 18 V range supports other supply conditions. The Schmitt-trigger clock input is valuable when the timing source has slow edges. Designers should still verify noise margins, output current, reset timing, and unused-input states against the manufacturer electrical-characteristics tables.
Recommended
Cyclic Lamp Chase
The ten decoded outputs of the CD4017BK can create a repeating lamp-chase or indication pattern in older counters, displays, and automation equipment. Connecting lamps or driver stages to Q0 through Q9 produces one active indication per clock transition, while reset returns the display to a defined position. The 11 MHz maximum operating frequency provides substantial timing headroom for low-rate visual sequences. Slow clock transitions are handled by the Schmitt-trigger input, although lamp-driver transistors should be used whenever the direct output current is insufficient. Firmware-based microcontrollers offer greater flexibility, but the CD4017BK provides a compact, autonomous hardware sequence without programmed logic.
Recommended
Pulse and Timing Signal Generation
The CD4017BK can generate selectable timing pulses by decoding successive counter states. The ten outputs provide phase-related signals that can be combined with gates, flip-flops, or discrete logic to produce repeating pulses or delayed events. Its maximum clock frequency of 11 MHz allows operation well beyond many low-frequency timing tasks, while the listed 650 ns propagation delay must be included in timing-chain budgets. Clock inhibit provides clean pause behavior, and reset synchronizes the sequence to a known condition. This approach is useful when a fixed hardware sequence is preferable to a programmable timer, especially in long-running control systems.
Recommended
Counter and Divider Module
The CD4017BK can serve as the central counter element in a larger divider, event-counter, or sequential logic module. Its rising-edge clock input processes incoming pulses, and the ten decoded states expose the count without requiring a binary decoder. The 3 V to 18 V operating range gives designers flexibility across nominal 5 V and higher-voltage CMOS systems. The CFP-16 ceramic flat package provides a through-hole assembly option for higher-temperature or ruggedized equipment when correctly rated. System designers should define all unused inputs, use pull-down or pull-up components where required, and account for reset priority and propagation delay when coordinating external logic.
Recommended
Recommended Products Summary
Engineering reference data for CD4017BK — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product |
|---|---|
| Counter Type | Decade counter with 10 decoded outputs |
| Supply Voltage Range | 3 V to 18 V |
| Nominal Supply Voltage | 5 V |
| Maximum Clock Frequency | 11 MHz |
| Propagation Delay | 650 ns |
| Clock Edge | Rising edge |
| Maximum Operating Temperature | 125 °C |
| Package | 16-lead CFP-16 ceramic flat package |
| Brand | Texas Instruments |
| Mounting Type | Through-hole ceramic flat package |
Key Differentiators
- Uses the distinct ceramic flat package rather than a DIP or small-outline package (vs CD4017BE)
- Supports a 3 V to 18 V CMOS supply range (vs CD4017BK)
- Provides ten decoded outputs with a listed 11 MHz maximum clock frequency (vs CD4017BCM)
Design Notes
Do not substitute CD4017BE or CD4017BCM directly for the CD4017BK. The BE version is a 16-PDIP package, while the BCM version is a small-outline surface-mount package. Both can implement the CD4017B function, but neither shares the CFP-16 footprint. A mechanical check and, where appropriate, a PCB or adapter redesign are required before substitution.
The clock input uses Schmitt-trigger action, allowing slow rising and falling edges, but the external clock source still needs a valid voltage range and clean transition timing. Avoid routing the clock adjacent to noisy relay-coil or switching-node traces. Include the listed 650 ns propagation delay when calculating feedback or cascaded-counter timing, particularly when Q9 is fed back to the clock input for divide-by-ten operation.
Design the board around the 16-lead CFP-16 footprint and verify pin one, lead spacing, ceramic-package dimensions, and the physical orientation against the manufacturer drawing. Keep the reset and clock-inhibit traces away from clock edges, and ensure every input has a defined logic state during power-up. Confirm whether a reset pull resistor is required for the intended startup sequence.
The CD4017BK operates from 3 V to 18 V with a nominal 5 V point. Decoupling capacitors should be placed close to VDD and VSS, with the exact capacitance selected from the manufacturer recommended operating conditions. Keep supply transients within the absolute maximum limits and account for dynamic current from multiple decoded outputs and external load circuitry when assessing the supply network.
Compliance Information
The available manufacturer product page and datasheet did not provide explicit RoHS, REACH, lead-free, halogen-free, or conflict-minerals status for the CD4017BK. AEC-Q100 is not applicable because this is a general-purpose CMOS logic counter rather than an automotive-qualified device.
