DS90C365MTDX - 85MHz LVDS FPD-Link Driver | TI
MPN: DS90C365MTDX ✓ ActiveDS90C365MTDX Overview
An LVDS transmitter is an interface IC that converts low-voltage digital data into a differential physical-layer signal. FPD-Link is a display-interface hierarchy in which parallel or encoded display data is transported over a low-voltage differential connection. Compared with single-ended drivers, LVDS uses complementary differential outputs to improve noise immunity, reduce sensitivity to common-mode noise, and support longer or higher-quality interconnects when implemented with appropriate termination and layout.
The DS90C365 supports a 3.3 V supply and 85 MHz signaling. The device family also includes DS90C385 and DS90C363 products, providing options for different channel-width and link requirements within the same FPD-Link application area. The DS90C365MTDX is identified as a one-driver FPD-Link LVDS device, while the 48-pin TSSOP package supports dense display-interface assemblies.
The transmitter is positioned for digital flat-panel displays, monitor backplanes, industrial display controllers, video timing conversion, and other systems that transmit display data between a controller and a panel. Its differential output architecture is especially useful where the cable or trace length makes common-mode noise rejection and signal integrity important.
For implementation, use the manufacturer's pin-description table when assigning signals and observe the recommended termination and decoupling arrangement. PCB routing should keep differential traces closely coupled, use controlled impedance, minimize stubs, and provide a continuous return path. Verify input timing, output mapping, supply sequencing, and panel-specific connector requirements before releasing a production layout.
This page consolidates the verified device identity, package information, interface characteristics, sourcing parameters, and application guidance into an engineering-oriented reference. It also identifies same-family drop-in candidates for design review, while clearly separating confirmed attributes from parameters that still require confirmation against the manufacturer datasheet.
Drop-in alternatives for DS90C365MTDX — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with DS90C365MTDX (same form factor and footprint) — differing in Package, Supply Voltage, Product Type, Input Data Width, Maximum Clock Frequency.
DS90C363BMTX
✅ Drop-InContact for price
View Datasheet →DS90C363BMTD
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
DS90C385MTDX
✅ Drop-In ⚠️ Specs UnverifiedContact for price
View Datasheet →DS90C385MTD
✅ Drop-In ⚠️ Specs UnverifiedContact for price
View Datasheet →DS90C365MTD
✅ Drop-In ⚠️ Specs UnverifiedContact for price
View Datasheet →DS90C365MTDX Specifications
| Product Type | Programmable LVDS FPD-Link transmitter |
| Supply Voltage | +3.3 V |
| Maximum Clock Frequency | 85 MHz |
| Data Channel Width | 18 bit |
| Signal Standard | LVDS |
| Interface Family | Flat Panel Display (FPD) Link |
| Driver Configuration | 1 driver |
| Number of Drivers | 1 |
| Number of Functions | 4 |
| Logic Family | CMOS |
| Package | 48-TSSOP |
| Pin Count | 48 pins |
| Mounting Type | Surface mount |
DS90C365MTDX 48-tssop Pin Configuration Guide
Pin configuration for DS90C365MTDX (48-tssop package). Pin numbering, functions, and connection diagrams are defined in the manufacturer datasheet. Refer to it for the exact footprint and soldering guidelines.
No detailed pinout data available for DS90C365MTDX.
Refer to the datasheet for full pin configuration.
Typical Applications
DS90C365MTDX is suitable for 6 applications: Flat-Panel Display Link, Industrial Display Controller, Video Timing Conversion, Monitor Backplane, Digital Signage Interface, LVDS Test and Measurement Interface.
Flat-Panel Display Link
The DS90C365MTDX fits a point-to-point Flat Panel Display Link because it combines an 18-bit data channel with LVDS signaling at up to 85 MHz. Place the transmitter between the display timing controller and panel receiver, then use the manufacturer-defined differential routing and termination arrangement. Its 48-pin TSSOP package provides adequate interface density for a dedicated display-link function, while the 3.3 V supply suits modern low-voltage controller logic. Before schematic release, confirm that the panel expects an 18-bit payload, the same clocking convention, and compatible data mapping. Also verify connector pin assignments and receiver termination because a shared footprint alone does not guarantee link interoperability.
Recommended
Industrial Display Controller
The DS90C365MTDX can serve as the panel-facing transmitter in an industrial display controller requiring a dedicated LVDS output stage. Its 18-bit channel and 85 MHz maximum clock provide a defined interface envelope for transferring display data over a board trace or shielded cable. Industrial suitability should be established using the exact temperature grade and reliability documentation for the released device. Keep the transmitter clock and data routing short and deterministic, provide the manufacturer's recommended decoupling, and maintain a continuous ground reference beneath the differential pair. Confirm receiver capabilities, input thresholds, and panel-specific mapping during controller bring-up rather than assuming compatibility from the FPD-Link label alone.
Recommended
Video Timing Conversion
DS90C365MTDX is applicable where a video timing converter must deliver display data through an LVDS panel link. The 18-bit transmitter channel supports the family's defined data organization, while the 85 MHz clock capability accommodates the target timing range. The transmitter should be connected according to the manufacturer's functional block diagram, with parallel source signals captured and serialized onto the differential outputs. Pay particular attention to clock polarity, enable timing, output mapping, and panel receiver requirements. For production hardware, test the worst-case pixel clock and data pattern across the complete cable and connector path to verify timing margin and signal integrity.
Recommended
Monitor Backplane
The DS90C365MTDX can be used in a monitor backplane that distributes panel data from a timing-control section to a display receiver. LVDS is appropriate where differential signaling and common-mode noise rejection are valuable in compact display electronics, particularly near switching regulators and high-speed digital circuitry. Route the transmitter outputs as a tightly coupled pair with a continuous reference plane, avoid unnecessary test pads and stubs, and place any receiver termination in accordance with the manufacturer interface guidance. The 48-pin TSSOP package requires careful assembly planning for adequate solder-joint formation and thermal relief around the pins. Validate the complete panel link at the maximum operating clock before approving the backplane layout.
Recommended
Digital Signage Interface
The DS90C365MTDX is appropriate for digital-signage electronics that transmit panel data from a controller board to an external or integrated LVDS display. Its 18-bit FPD-Link organization and 85 MHz operating point provide a defined basis for link design, while the 3.3 V supply simplifies integration with modern digital controllers. Digital-signage systems often include long cable runs, so use only interfaces approved for the target cable length and apply the specified receiver termination. Keep power converters and switching nodes away from the differential outputs, maintain a solid ground plane, and verify eye margin, skew, and clock recovery at the receiver. Panel data mapping must match the sign controller configuration.
Recommended
LVDS Test and Measurement Interface
DS90C365MTDX can provide the transmitter side of an LVDS test fixture or measurement interface intended to exercise FPD-Link-compatible receivers. Using an 18-bit channel at up to 85 MHz enables representative link traffic for checking receiver timing, data capture, and display-controller behavior. Build the fixture with controlled-impedance routing, clean reference planes, and the manufacturer's recommended output network. Use controlled patterns to investigate data-dependent errors and timing margins instead of relying only on a static image. Because the transmitter and cable form one complete channel, document cable length, connector type, receiver termination, and test conditions so results can be reproduced. Confirm that the intended receiver accepts the same payload organization and clocking scheme.
Recommended
Recommended Products Summary
Engineering reference data for DS90C365MTDX — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | DS90C363BMTX | DS90C363BMTD | DS90C385MTDX | DS90C385MTD | DS90C365MTD |
|---|---|---|---|---|---|---|
| Package | 48-TSSOP | 48-TSSOP | 48-TSSOP | 48-TSSOP | 48-TSSOP | 48-TSSOP |
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Product Type | Programmable LVDS FPD-Link transmitter | FPD-Link transmitter | FPD-Link transmitter | +3.3 V programmable LVDS transmitter | +3.3 V programmable LVDS transmitter | +3.3 V programmable LVDS transmitter |
| Signal Standard | LVDS | FPD-Link LVDS | LVDS | LVDS | LVDS | LVDS |
| Pin Count | 48 pins | 48 pins | 48 pins | 48 pins | 48 pins | 48 pins |
Key Differentiators
- Targeted 18-bit FPD-Link data organization (vs DS90C385MTDX)
- Defined 85 MHz FPD-Link operating point (vs DS90C363BMTX)
- Dedicated one-driver FPD-Link implementation (vs DS90C363BMTD)
Design Notes
Route the LVDS outputs as a tightly coupled differential pair on a continuous reference plane. Use the manufacturer-recommended receiver termination and preserve the specified impedance through connectors or cable transitions. Avoid stubs and unnecessary test pads on the high-speed outputs. Because the device supports operation to 85 MHz, validate eye margin and timing at the intended pixel clock with the production cable, connector, receiver, and data pattern rather than relying only on simulation.
Assign the 48-pin TSSOP connections directly from the manufacturer pin-description table and verify pin-1 orientation before fabrication. Place local supply decoupling at the device power pins and keep the return-current path continuous beneath the differential pair. Isolate the LVDS outputs from switching-node currents and noisy inductors. If the design includes another FPD-Link transmitter, maintain consistent channel spacing and termination geometry across all parallel links.
Do not infer interchangeability from the shared 48-TSSOP package or from the FPD-Link family name. Before replacing the DS90C365MTDX, compare pin-to-pin enable timing, clock polarity, data mapping, channel width, maximum clock, output network, and power requirements. The DS90C385 family is identified as 24-bit, while the target is 18-bit, so choosing it may require logic or panel-interface changes even when the package is unchanged.
Design the 3.3 V rail to support both the transmitter and the load presented by its associated interface circuitry. Follow the manufacturer recommendations for supply bypass capacitance and placement. When the transmitter is adjacent to switching power stages, account for conducted and radiated coupling in the board stack-up and keep high di/dt loops away from the differential outputs. Confirm startup, enable sequencing, and voltage tolerance against the device electrical characteristics before production release.
Compliance Information
The available product information does not establish the requested compliance declarations or automotive qualification status. Verify current declarations with Texas Instruments before procurement.
