DSPIC33CK128MC506-E/MR - 16-bit 100MHz DSC CAN FD | Microchip
MPN: DSPIC33CK128MC506-E/MR ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $5.2 | $5.20 |
| 10 | $4.75 | $47.50 |
| 100 | $4.2 | $420.00 |
| 500 | $3.85 | $1,925.00 |
| 1,000 | $3.5 | $3,500.00 |
DSPIC33CK128MC506-E/MR Overview
A digital signal controller combines the computational capability of a digital signal processor with the control peripherals of a microcontroller on a single silicon die. Within the embedded control hierarchy, the DSC sits between general-purpose MCUs and dedicated DSPs, making the dsPIC33CK family well suited for control loops that need both fast math and rich analog and timing peripherals.
Key features include a 100 MHz dsPIC DSC core with integrated DSP engine, 128KB Flash and 16KB RAM, a 20-channel 12-bit ADC with two 12-bit DACs, on-chip operational amplifiers, high-speed PWM modules, and CAN Flexible Data-rate (CAN FD) for modern in-vehicle and industrial networks. 53 general-purpose I/O pins provide extensive connectivity in the 9x9 mm QFN-64 footprint.
Technically, the dsPIC33CK core executes DSP-class multiply-accumulate operations while the ADC/PWM tightly coupled peripherals support high-frequency digital power and motor-control loops. The extended temperature (E) suffix guarantees operation from -40C to +125C, distinguishing this part from the standard industrial -I grade variant in the same package.
Typical applications include digital power supplies (totem-pole PFC, LLC converters), brushless DC and PMSM motor control, automotive and industrial CAN FD nodes, and advanced sensing and control systems that exploit the on-chip op amps and 12-bit converter pair.
Design consideration: the 3.0V to 3.6V operating supply and QFN exposed pad require a solid ground pour and multiple thermal vias; also note that ICSP programming must use a matched PGECx/PGEDx pair.
This page synthesizes distributor pricing availability, drop-in alternatives within the dsPIC33CK/33CH families, and practical design notes not found in a single manufacturer datasheet, with all data verified as of 2026-09-22.
Drop-in alternatives for DSPIC33CK128MC506-E/MR — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with DSPIC33CK128MC506-E/MR (same form factor and footprint) — differing in Operating Temperature, Core, PWM, Operating Voltage.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
DSPIC33CK128MC506-I/MR
✅ Drop-In📋 Reference alternative (not in catalog)
DSPIC33CK256MC506-I/MR
✅ Drop-In ⚠️ Specs Unverified✓ In Stock
$3.92 / Unit
View Datasheet →DSPIC33CK64MC506-I/MR
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
DSPIC33CK128MP506-I/MR
✅ Drop-In✓ In Stock
$4.35 / Unit
View Datasheet →DSPIC33CH64MP506T-I/MR
✅ Drop-In📋 Reference alternative (not in catalog)
DSPIC33CK128MC506-E/MR Maximum Ratings & Electrical Characteristics
| Core | dsPIC33CK 16-bit DSC core |
| Maximum Operating Frequency | 100 MHz |
| Program Memory (Flash) | 128KB (128K x 8) |
| Data Memory (RAM) | 16KB |
| Operating Voltage | 3 V to 3.6 V |
| General-Purpose I/O | 53 I/O |
| ADC Resolution | 12-bit |
| ADC Channels | 20-channel |
| DAC | 2 x 12-bit |
| CAN Interface | CAN FD |
| PWM | High-speed PWM |
| On-chip Op Amps | Yes |
| Package | 64-QFN (9x9 mm) |
| Operating Temperature | -40C to +125C (extended, E grade) |
| Mounting Type | Surface Mount |
| Series | dsPIC33CK, Functional Safety (FuSa) |
| RoHS Status | Compliant |
DSPIC33CK128MC506-E/MR 64-qfn (9x9 mm) Pin Configuration Guide
Pin configuration for DSPIC33CK128MC506-E/MR (64-qfn (9x9 mm) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for DSPIC33CK128MC506-E/MR.
Refer to the datasheet for full pin configuration.
Typical Applications
DSPIC33CK128MC506-E/MR is suitable for 6 applications: Digital Power Supplies, Brushless DC and PMSM Motor Control, Automotive and Industrial CAN FD Nodes, Advanced Sensing and Control Systems, High-Performance General Embedded Control, Wireless Power Transfer and Charging Control.
Digital Power Supplies
The DSPIC33CK128MC506-E/MR fits digital power conversion because its 100 MHz dsPIC DSC core closes current-mode control loops fast enough for totem-pole PFC and LLC topologies, while the high-speed PWM module provides complementary outputs with programmable dead time and phase shifting. The 20-channel 12-bit ADC samples input voltage, output voltage, and inductor current, and the two 12-bit DACs can generate reference or bias levels. Used as the digital controller between the power stage gate drivers and the feedback divider, it replaces analog control ICs with firmware-defined compensation, adding adaptive mode switching and telemetry over CAN FD. The trade-off versus analog control is firmware complexity and the need to budget ADC sampling and ISR execution within each switching period at the 100 MHz core rate.
Recommended
Brushless DC and PMSM Motor Control
The DSPIC33CK128MC506-E/MR is designed for motor control: Microchip explicitly targets the dsPIC33CK family at motor control designs. The 100 MHz core executes field-oriented control (FOC) math using the integrated DSP multiply-accumulate engine, the high-speed PWM drives six-step or SVPWM inverter stages with hardware dead-time insertion, and the 20-channel 12-bit ADC captures three-phase currents and DC bus voltage. On-chip operational amplifiers condition low-side shunt signals, reducing external component count, and the CAN FD interface links the drive into industrial networks. With 53 GPIO, encoder and Hall interfaces connect directly. Performance consideration: keep the FOC current-loop ISR within the ADC-to-PWM trigger period; the extended -40C to +125C E grade suits motor-drive enclosures that heat beyond industrial limits.
Recommended
Automotive and Industrial CAN FD Nodes
The DSPIC33CK128MC506-E/MR serves as a smart CAN FD node in vehicles and factory equipment. Its integrated CAN Flexible Data-rate controller supports the higher data-phase bitrates and up to 64-byte payloads of the CAN FD standard, while the -40C to +125C extended E temperature grade tolerates under-hood and sealed-enclosure environments. The 20-channel 12-bit ADC digitizes local sensors, the DSP core filters and interprets the data, and 53 GPIO drive actuators or indicator circuits, all powered from a 3.0-3.6V rail typical of automotive electronics. Because the dsPIC33CK family carries Functional Safety (FuSa) packaging options per the family listing, safety-related node development is supported. Design consideration: route the CAN FD transceiver within centimeters of the CANTX/CANRX pins and honor the matched PGECx/PGEDx pairing for in-system programming.
Recommended
Advanced Sensing and Control Systems
The DSPIC33CK128MC506-E/MR fits advanced sensing nodes that combine multiple analog inputs with local decision-making. The 20-channel 12-bit ADC with 2x 12-bit DAC and on-chip op amps implements sensor excitation, signal conditioning, and conversion in one 64-QFN device, while the 100 MHz DSP core performs FFT or filtering on the sampled streams. Typical deployments include vibration monitoring, precision process control, and multi-zone environmental sensing where the 128KB Flash holds both the control firmware and compensation tables. CAN FD connectivity streams results to supervisory controllers without an external communication chip. The performance consideration is analog front-end layout: keep ADC input traces short and reference the converter to a clean ground island under the exposed pad to preserve 12-bit accuracy.
Recommended
High-Performance General Embedded Control
For general embedded systems needing more than a mid-range MCU, the DSPIC33CK128MC506-E/MR supplies a 100 MHz 16-bit core with DSP capability, 128KB Flash, and 16KB RAM in a compact 9x9 mm QFN-64. Compared with a conventional microcontroller, the DSC adds single-cycle multiply-accumulate for audio processing, digital filtering, and control math, while retaining standard peripherals: 53 GPIO, timers, UART/SPI/I2C, PWM, and CAN FD. It suits robotics controllers, instrumentation front ends, and communication bridges where deterministic interrupt latency matters. The extended -40C to +125C rating removes ambient-temperature constraints common in industrial enclosures. Memory consideration: applications needing larger code space should select the pin-compatible DSPIC33CK256MC506 rather than redesigning the board.
Recommended
Wireless Power Transfer and Charging Control
The DSPIC33CK128MC506-E/MR is well matched to wireless power transmitter and receiver control. Frequency-tracking resonant converters demand fast PWM frequency adjustment, which the high-speed PWM module performs with fine resolution at the 100 MHz core rate, while the 20-channel 12-bit ADC monitors coil current, foreign-object detection voltage signatures, and temperature simultaneously. The DSP engine implements the tracking and Q-factor algorithms, and the CAN FD interface reports charging status in automotive wireless charging systems where the -40C to +125C E grade survives the pad environment. The two 12-bit DACs provide controllable reference thresholds for fault comparators. Performance consideration: budget the foreign-object detection scan between power-transfer frames so sampling does not distort the resonant waveform.
Recommended
Recommended Products Summary
Engineering reference data for DSPIC33CK128MC506-E/MR — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | DSPIC33CK128MC506-I/MR | DSPIC33CK256MC506-I/MR | DSPIC33CK64MC506-I/MR | DSPIC33CK128MP506-I/MR | DSPIC33CH64MP506T-I/MR |
|---|---|---|---|---|---|---|
| Package | 64-QFN (9x9 mm) | 64-QFN (9x9 mm) - same | 64-QFN (9x9 mm) - same | 64-QFN (9x9 mm) - same | 64-QFN (9x9 mm) - same | 64-QFN (9x9 mm) - same |
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| Core Speed | 100 MHz | 100 MHz | 100 MHz | 100 MHz | 100 MHz | 100 MHz (dual core) |
| Flash | 128KB | 128KB | 256KB | 64KB | 128KB | 64KB |
| Temperature Range | -40C to +125C (E grade) | -40C to +85C (I grade) | -40C to +85C (I grade) | -40C to +85C (I grade) | -40C to +85C (I grade) | -40C to +85C (I grade) |
| Architecture | Single-core dsPIC33CK DSC | Single-core dsPIC33CK | Single-core dsPIC33CK | Single-core dsPIC33CK | Single-core dsPIC33CK | Dual-core dsPIC33CH (master+slave) |
| CAN FD | Yes | Yes | Yes | Yes | Yes | Yes |
Key Differentiators
- Extended -40C to +125C temperature grade (vs DSPIC33CK128MC506-I/MR)
- Balanced 128KB Flash at MC506 cost point (vs DSPIC33CK256MC506-I/MR)
- Single-core simplicity versus dual-core dsPIC33CH (vs DSPIC33CH64MP506T-I/MR)
Design Notes
The 64-QFN (9x9 mm) package has an exposed thermal pad that must be soldered to a ground pour with an array of thermal vias (typically 5x5 via grid) to achieve reliable grounding and heat dissipation, particularly for the E-grade device operating up to +125C junction environments. Fan out the 53 GPIO with short traces to the ADC inputs, and reserve space for the 3.0-3.6V supply decoupling network - place 100 nF ceramic capacitors at each supply pin pair plus one bulk capacitor per rail.
ICSP programming requires a matched PGECx/PGEDx clock-data pair: if PGEC2 carries ICSPCLK, PGED2 must carry ICSPDAT - mismatched pairs will fail programming, per the dsPIC33CK128MC506 development guidance from northernsoftware.com. Additionally, do not substitute the -I grade part where ambient exceeds +85C; the E/MR variant is the only correct choice for -40C to +125C environments. Finally, MCLR-based programming voltages must be isolated from other circuitry during in-circuit flash.
Operating from 3.0V to 3.6V, the digital core switching noise couples into the 12-bit ADC references. Estimate: at 100 MHz the core draws in the tens-of-mA range; add margin in your 3.3V regulator budget for all 53 I/O loaded. Recommended practice from Microchip reference designs for the dsPIC33CK family: separate the analog 3.3V entry through an LC filter (ferrite bead plus 10 uF) feeding the VDDCORE/VDD analog domain, and tie the ADC reference to a quiet ground island directly beneath the exposed pad.
Compliance Information
RoHS compliance stated by distributor listings for the dsPIC33CK family; REACH, lead-free and halogen-free detail not stated in provided data - verify on Microchip's product page.
