DSPIC33EP128GS702T-I/MM - 16-bit DSC 70 MIPS 128KB Flash | Microchip
MPN: DSPIC33EP128GS702T-I/MM ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $5.75 | $5.75 |
| 10 | $5.2 | $52.00 |
| 100 | $4.68 | $468.00 |
| 500 | $4.3 | $2,150.00 |
| 1,000 | $3.95 | $3,950.00 |
DSPIC33EP128GS702T-I/MM Overview
A digital signal controller combines the compute power of a DSP engine with the control peripherals and ease of use of a microcontroller. In the system hierarchy, a DSC sits between a general-purpose MCU and a dedicated DSP: it executes deterministic control loops and mathematical routines (PID, transforms, filters) while integrating ADCs, PWM modules and serial ports on one chip. This makes DSCs the dominant choice in digital power conversion and motor control.
The GS702 belongs to Microchip's dsPIC33EP GS family, purpose-built for switch-mode power supplies (SMPS) and digital power conversion. Key features include a high-speed 16-bit pipelined core with DSP instruction support, a high-resolution PWM module suited to multi-loop converter topologies, and a fast analog-to-digital converter for current-mode control sampling. Seven timers and four serial I/O ports provide the scheduling and communications backbone for embedded power products.
Architecturally, the device uses a modified Harvard pipeline with 24-bit instruction words, hardware multiply-accumulate (MAC) and divide support, enabling per-sample control-loop execution at switching frequencies well into the hundreds of kilohertz. The -I suffix denotes the industrial temperature grade; the T suffix denotes tape-and-reel delivery for automated assembly.
Typical applications include AC-DC and DC-DC digital power supplies, power factor correction stages, solar micro-inverters, BLDC and PMSM motor drives, and UPS systems.
Design consideration: the QFN exposed pad doubles as the primary thermal and ground path, so connect it to a solid ground plane with multiple thermal vias; decouple VDD and the VCAP pin per the family datasheet DS70005258C.
This page synthesizes distributor pricing, drop-in family alternatives, and practical design notes not found in the manufacturer datasheet, verified as of 2026-09-23.
Drop-in alternatives for DSPIC33EP128GS702T-I/MM — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with DSPIC33EP128GS702T-I/MM (same form factor and footprint) — differing in Operating Temperature, Package, RAM, Core, Functional Safety Support.
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Request AlternativesDSPIC33EP128GS702T-I/MM Maximum Ratings & Electrical Characteristics
| Core Architecture | 16-bit dsPIC33EP DSC with DSP engine |
| Maximum MIPS | 70 MIPS |
| Flash Program Memory | 128 KB (43K x 24) |
| RAM | 8 KB |
| Supply Voltage | 3.3 V |
| Package | 28-QFN-S (6 x 6 mm), exposed pad |
| Mounting Type | Surface Mount |
| Operating Temperature | -40C to +85C (industrial, -I grade) |
| Timers | 7 |
| Serial I/O Ports | 4 |
| Product Family | dsPIC33EPXXXGS70X/80X (SMPS & Digital Power Conversion) |
| Functional Safety Support | Yes (FuSa classified per DigiKey) |
| Packaging Suffix | T (Tape and Reel) |
| Program Memory Width | 24-bit instruction word |
| Process Technology | CMOS |
DSPIC33EP128GS702T-I/MM Pin Configuration
| Pin 1 | MCLR — Master clear reset input / programming voltage |
| Pin 2 | AN0/VREF+/CN0/RB0 — Analog input 0 / positive ADC reference / change notification |
| Pin 3 | AN1/VREF-/CN1/RB1 — Analog input 1 / negative ADC reference / change notification |
| Pin 4 | AN2/SS1/LVDIN/CN2/RB2 — Analog input 2 / SPI slave select / low-voltage detect input |
| Pin 5 | AN3/INDX/CN3/RB3 — Analog input 3 / QEI index input / change notification |
| Pin 6 | AN4/QEA/REFO/CN4/RB4 — Analog input 4 / QEI phase A / reference clock output |
| Pin 7 | AN5/QEB/CN5/RB5 — Analog input 5 / QEI phase B / change notification |
| Pin 8 | VSS — Ground reference |
| Pin 9 | VDD — Positive supply (3.3 V) |
| Pin 10 | OSC1/CLKI/RA2 — Crystal oscillator input / external clock input |
| Pin 11 | OSC2/CLKO/RC15 — Crystal oscillator output / clock output |
| Pin 12 | PGED1/RP1/RC1 — In-circuit debug data / remappable peripheral pin 1 |
| Pin 13 | PGEC1/RP0/RC0 — In-circuit debug clock / remappable peripheral pin 0 |
| Pin 14 | AN8/CN8/RB6 — Analog input 8 / change notification |
| Pin 15 | AN9/CN9/RB7 — Analog input 9 / change notification |
| Pin 16 | AN10/CN10/RB8 — Analog input 10 / change notification |
| Pin 17 | AN11/SDA1/CN11/RB9 — Analog input 11 / I2C data / change notification |
| Pin 18 | AN12/SCL1/CN12/RB10 — Analog input 12 / I2C clock / change notification |
| Pin 19 | AN13/INT0/CN13/RB11 — Analog input 13 / external interrupt 0 |
| Pin 20 | AN14/CN14/RB12 — Analog input 14 / change notification |
| Pin 21 | AN15/OCFB/CN15/RB13 — Analog input 15 / complementary PWM fault input |
| Pin 22 | VCAP/VDDCORE — Core voltage regulator capacitor connection |
| Pin 23 | VDD — Positive supply (3.3 V) |
| Pin 24 | VSS — Ground reference |
| Pin 25 | RP10/RF4/U1RX — Remappable pin / UART1 receive |
| Pin 26 | RP11/RF5/U1TX — Remappable pin / UART1 transmit |
| Pin 27 | RP19/RF1/PWM1L — Remappable pin / PWM1 low-side output |
| Pin 28 | RP18/RF0/PWM1H — Remappable pin / PWM1 high-side output |
Typical Applications
DSPIC33EP128GS702T-I/MM is suitable for 6 applications: Digital AC-DC Power Supplies, DC-DC Converters and Point-of-Load Rails, Power Factor Correction (PFC) Stages, Solar Micro-Inverters, BLDC and PMSM Motor Drives, Uninterruptible Power Supplies (UPS).
Digital AC-DC Power Supplies
The DSPIC33EP128GS702T-I/MM is designed specifically for digitally controlled AC-DC converters, replacing analog compensation networks with firmware PID loops executed at 70 MIPS. Its GS-family high-resolution PWM allows fine duty-cycle and phase adjustment for LLC, flyback and forward topologies, while the fast on-chip ADC samples input/output voltage and inductor current synchronously with the PWM carrier. Placed as the sole supervisory controller, it implements startup sequencing, soft-start, burst mode and fault protection in software, cutting BOM count versus discrete analog controllers. The 128 KB Flash accommodates multiple converter profiles plus communication firmware, and the industrial -40C to +85C rating suits enclosed PSU environments.
Recommended
DC-DC Converters and Point-of-Load Rails
For telecom rectifiers, server VRMs and industrial DC-DC bricks, the GS702 provides per-rail digital control with deterministic loop latency. Running its compensation loop at hundreds of kilohertz, the 16-bit DSP core with MAC instructions computes PID or 2p2z compensators within one switching period, while the high-resolution PWM module sets precise duty and dead time for synchronous buck or boost stages. The 8 KB RAM retains transient buffers for telemetry and tuning, and the four serial ports interface to PMBus-like supervisory links. Firmware-defined gains allow a single PCB to serve multiple output voltages, reducing SKU proliferation; the exposed-pad QFN conducts switching-stage heat into the ground plane.
Recommended
Power Factor Correction (PFC) Stages
In boost-PFC front ends, the DSPIC33EP128GS702T-I/MM executes average-current-mode control with input-voltage feedforward, maintaining high power factor and low THD across universal AC input. The 70 MIPS core closes both the fast inner current loop and the slow outer voltage loop on one device, while the high-resolution PWM shapes duty waveforms that follow the rectified sine reference. On-chip ADC channels sample the AC zero crossing and bus voltage for feedforward and brown-out handling, and firmware implements inrush limiting and cycle-by-cycle current limits. The 128 KB Flash stores harmonic-compensation tables and protection state machines, meeting digital-power design goals that analog PFC controllers handle only with external circuitry.
Recommended
Solar Micro-Inverters
Micro-inverters require MPPT algorithms, grid-synchronization and inverter PWM control concurrently - a workload the GS702 handles at 70 MIPS with its DSP MAC pipeline. The controller samples panel voltage/current through the fast ADC for perturb-and-observe MPPT, generates a synchronized PWM drive for the DC-AC stage, and runs anti-islanding protection in firmware. Its 128 KB Flash holds grid-code tables for multiple regions, and the four serial ports support power-line-communication or RF gateway interfaces for monitoring. The industrial temperature grade and small 6 x 6 mm QFN suit the sealed, thermally stressed enclosure of a panel-mounted micro-inverter, where board area is at a premium.
Recommended
BLDC and PMSM Motor Drives
The GS702 drives sensorless BLDC and PMSM motors using field-oriented control (FOC): the DSP engine computes Clarke/Park transforms and PI current loops each PWM cycle, while the high-resolution PWM module produces complementary six-step or SVPWM outputs with programmable dead time. The fast ADC samples phase currents at the PWM midpoint to avoid switching noise, and firmware back-EMF observers estimate rotor position without hall sensors, cutting sensor cost. The 128 KB Flash supports trajectory profiles and CAN or UART fieldbus stacks on the four serial ports. Seven timers handle encoder capture, speed measurement and housekeeping, making a single DSC sufficient for a complete compact drive.
Recommended
Uninterruptible Power Supplies (UPS)
Line-interactive and online UPS products use the DSPIC33EP128GS702T-I/MM to coordinate battery charging, inverter output regulation and transfer-switch logic on one chip. The 70 MIPS core runs nested control loops for the inverter stage while supervising charger current and bus voltage through the multi-channel ADC; deterministic interrupt latency keeps output distortion low during mode transitions. Firmware in the 128 KB Flash implements battery health algorithms, self-test and event logging, and serial ports provide SNMP or Modbus reporting for rack monitoring. The industrial temperature range covers equipment-room ambients, and the exposed-pad QFN-28 footprint keeps the controller section compact on dense power boards.
Recommended
Recommended Products Summary
Engineering reference data for DSPIC33EP128GS702T-I/MM — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | DSPIC33EP128GS702T-E/MM | DSPIC33EP64GS702T-I/MM | DSPIC33EP128MC202-I/MM |
|---|---|---|---|---|
| Package | 28-QFN-S (6 x 6 mm), exposed pad | 28-QFN-S (6 x 6 mm) - same | 28-QFN-S (6 x 6 mm) - same | 28-QFN-S (6 x 6 mm) - same |
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| Core / Speed | 16-bit dsPIC33EP, 70 MIPS | 16-bit, 70 MIPS | 16-bit, 70 MIPS | 16-bit, 70 MIPS |
| Flash Memory | 128 KB (43K x 24) | 128 KB (43K x 24) | 64 KB | 128 KB |
| RAM | 8 KB | 8 KB | 8 KB | 8 KB |
| Temperature Range | -40C to +85C (industrial, -I) | Extended grade (-E) | -40C to +85C | -40C to +85C |
| Peripheral Focus | SMPS / digital power (GS): high-res PWM + fast ADC | SMPS / digital power (GS) - identical | SMPS / digital power (GS) - identical | Motor control (MC) PWM/ADC set |
Key Differentiators
- SMPS-optimized analog and PWM peripheral set (vs DSPIC33EP128MC202-I/MM)
- Full 128 KB Flash for feature-rich digital power firmware (vs DSPIC33EP64GS702T-I/MM)
- Industrial temperature qualification with extended-grade upgrade path (vs DSPIC33EP128GS702T-E/MM)
Design Notes
The exposed pad on the 28-QFN-S (MM) package is the primary ground and thermal path - do not leave it unconnected for prototyping convenience. Define a ground keepout with a 3x3 (or larger) array of thermal vias (0.3 mm drill, filled or tented) down to the internal ground plane. The QFN 0.9 mm package height demands an accurate stencil: use approximately 50-70% paste coverage on the center pad to avoid voiding and component float. Per family datasheet DS70005258C, follow the recommended QFN land pattern for the 6 x 6 mm body.
Decouple each VDD pin with 100 nF ceramic capacitors placed within 2 mm of the pin, plus one bulk 4.7-10 uF capacitor near the device. The VCAP/VDDCORE pin requires the internal regulator stabilization capacitor specified in DS70005258C - do not load this pin with external circuitry and observe the stated capacitance and ESR range, or the core regulator may become unstable during Flash write operations. Estimated: at 70 MIPS the core current draw is in the tens of mA range, so IR drop on a solid ground plane is negligible, but switching-node coupling into VCAP traces can corrupt analog readings.
Configure unused ANx pins as digital outputs driving low, or as inputs with pull-ups, per Microchip I/O guidance - floating analog-capable pins on RB0-RB13 increase supply current and can pick up noise that corrupts ADC results. Remember that PGEC1/PGED1 on pins 12/13 must remain routable to a programming header (or standard 5-pin ICSP connector) even in production boards, otherwise in-field firmware updates become impossible. Peripherals are remappable via PPS - document your RPn assignments, since conflicting PPS maps are a common bring-up failure.
For digital-power applications, keep the ADC input traces (AN0-AN15) away from PWM high-side switching nodes and gate-drive traces by at least 3x trace width, or guard them with ground. Sample current feedback at the PWM midpoint (center-aligned trigger) rather than free-running to avoid switching-transient corruption - the GS-family ADC supports PWM-triggered conversion for exactly this purpose. Route the oscillator (OSC1/OSC2) with short, symmetric traces and guard with ground if an external crystal is used.
Compliance Information
Compliance status was not stated in the verified web data; Microchip standard catalog parts are typically RoHS-compliant, but confirm on the official Microchip product page or datasheet DS70005258C before procurement.
