DSPIC33FJ128GP706AT-I/MR - 16-bit DSC 128KB 40MIPS 64-QFN | Microchip
MPN: DSPIC33FJ128GP706AT-I/MR ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $7.06 | $7.06 |
| 10 | $6.6 | $66.00 |
| 100 | $6.2 | $620.00 |
| 500 | $5.9 | $2,950.00 |
| 1,000 | $5.6 | $5,600.00 |
DSPIC33FJ128GP706AT-I/MR Overview
A digital signal controller combines the peripherals and ease of use of a microcontroller with the computational throughput of a DSP core, sitting in the product hierarchy between a general-purpose MCU (such as a PIC18) and a dedicated DSP. The dsPIC33F family implements a modified Harvard, 16-bit architecture that executes most instructions in a single cycle, with DSP-class multiply-accumulate (MAC), barrel shifter, and modulo/bit-reversed addressing for signal-processing kernels.
Key features of this device include 128KB (132KB equivalent, 128K x 8) of self-programmable flash, 40 MIPS sustained instruction throughput at 3.3V, industrial temperature operation from -40C to +85C, and a rich analog and digital peripheral set typical of the GP (general purpose) family: 10-/12-bit ADC channels, UART, SPI, I2C, input capture/output compare modules, and motor-control-capable PWM when configured through the shared peripheral matrix. The A-series silicon revision improves errata coverage over the original dsPIC33FJ128GP706.
Architecturally, the dsPIC33F core provides two 40-bit wide accumulators, 17-bit x 17-bit single-cycle hardware multiplier, and dual operand fetch, enabling efficient FIR/IIR filtering, FFT execution, and control-loop computation at fixed 40 MIPS. The device supports in-circuit serial programming (ICSP) and debugging via PGD/PGC pins, boundary scan capability, and a flexible clock tree with PLL from an external crystal or internal FRC oscillator.
Typical applications include digital power supplies, motor control drives, sensor signal conditioning with on-chip DSP post-processing, industrial automation nodes, and audio/signal-processing front ends where a single DSC replaces separate MCU plus DSP chips.
For design, budget the 3.0V-3.6V rail carefully: 40 MIPS operation is specified over the full voltage range, but place 0.1uF decoupling at every VDD pin and use the exposed pad as the primary ground return for lowest noise. The tape-and-reel T suffix supports automated assembly.
This page synthesizes distributor pricing from LCSC and Heisener, drop-in same-package alternatives across the dsPIC33FJ128GP706A family, and practical design notes not found in the manufacturer datasheet, with pricing as of 2026-09-26.
Drop-in alternatives for DSPIC33FJ128GP706AT-I/MR — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with DSPIC33FJ128GP706AT-I/MR (same form factor and footprint) — differing in Family, Operating Temperature, Package, Packaging Option, RoHS Status.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
DSPIC33FJ128GP706AT-E/MR
✅ Drop-In📋 Reference alternative (not in catalog)
DSPIC33FJ128GP706ATH/MR
✅ Drop-In📋 Reference alternative (not in catalog)
DSPIC33FJ128GP706T-I/MR
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
DSPIC33FJ128GP706A-I/MR
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
DSPIC33FJ256GP706AT-I/MR
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
DSPIC33FJ64GP706AT-I/MR
✅ Drop-In ⚠️ Specs Unverified✓ In Stock
$5 / Unit
View Datasheet →DSPIC33FJ128GP706AT-I/MR Maximum Ratings & Electrical Characteristics
| Core Architecture | 16-bit dsPIC33F DSC |
| Program Memory (Flash) | 128KB |
| Instruction Throughput | 40 MIPS |
| Clock Frequency | 40 MHz |
| Supply Voltage Range | 3 V to 3.6 V |
| Operating Temperature | -40C to +85C (Industrial, I) |
| Package | 64-VFQFN Exposed Pad, 9x9 mm (MR) |
| Mounting Type | Surface Mount |
| Number of Pins/Terminals | 64 |
| Core Type | CMOS, modified Harvard 16-bit |
| DSP Features | Single-cycle MAC, barrel shifter, dual 40-bit accumulators |
| Family | dsPIC33FJ128GP706A (GP series) |
| Programming / Debug | ICSP via PGD/PGC, boundary scan |
| Packaging Option | Tape and Reel (T suffix) |
| RoHS Status | Compliant (per JLCPCB listing) |
| External Interfaces | UART, SPI, I2C, capture/compare, PWM (GP peripheral set) |
DSPIC33FJ128GP706AT-I/MR 64-vfqfn exposed pad, 9x9 mm (mr) Pin Configuration Guide
Pin configuration for DSPIC33FJ128GP706AT-I/MR (64-vfqfn exposed pad, 9x9 mm (mr) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for DSPIC33FJ128GP706AT-I/MR.
Refer to the datasheet for full pin configuration.
Typical Applications
DSPIC33FJ128GP706AT-I/MR is suitable for 6 applications: Digital Power Supplies, Industrial Motor Control Drives, Sensor Signal Conditioning with DSP Post-Processing, Industrial Automation and Control Nodes, Audio and Signal-Processing Front Ends, Embedded Systems Education and Prototyping.
Digital Power Supplies
The DSPIC33FJ128GP706AT-I/MR fits digitally controlled AC-DC and DC-DC converters because its 40 MIPS fixed-point core executes voltage-mode and current-mode compensation loops at 100 kHz-plus switching frequencies with deterministic single-cycle MAC latency. The dual 40-bit accumulators and barrel shifter handle PI/PID and notch-filter kernels without floating-point overhead, while GP-family capture/compare and PWM resources generate complementary gate drives with resolution adequate for phase management. In a typical topology, the DSC samples the output via the ADC and updates the PWM duty register each cycle; the 3.0V-3.6V rail and 64-QFN exposed pad give a low-inductance ground that resists switching-noise corruption of analog sensing. Firmware upgradability over fixed-function controllers is the key trade-off benefit.
Recommended
Industrial Motor Control Drives
For BLDC, PMSM, and ACIM drives, the DSPIC33FJ128GP706AT-I/MR provides the 40 MIPS throughput needed to run field-oriented control (FOC) at multi-kHz current-loop rates while simultaneously handling UART or CAN-class communication. The 17x17 single-cycle multiplier and dual 40-bit accumulators compute Clarke/Park transforms and PI current regulators with fixed-point determinism, avoiding the jitter of interrupt-heavy software FP. GP peripheral capture/compare modules generate the six-channel inverter gating with dead-time control. Housed in a 64-VFQFN exposed-pad package rated -40C to +85C, it mounts directly on the control PCB adjacent to gate drivers; the exposed pad anchors a solid ground plane that keeps inverter switching noise out of ADC sense lines.
Recommended
Sensor Signal Conditioning with DSP Post-Processing
The DSPIC33FJ128GP706AT-I/MR replaces separate MCU-plus-DSP chains in smart sensors by acquiring analog signals through its integrated ADC and applying FIR/IIR filtering, FFT-based analysis, or RMS computation on-chip at 40 MIPS. The 128KB flash accommodates calibration tables, coefficient sets, and communication stacks simultaneously, and the A-series silicon revision improves errata maturity for long-lifetime industrial instruments. Because the GP peripheral set multiplexes UART, SPI, and I2C onto shared pins, one 64-QFN device can stream processed results over multiple buses while retaining capture/compare channels for event timestamping. The main design consideration is analog front-end layout: keep sense traces short to the ADC pins and use the exposed pad as the star ground reference to preserve effective converter resolution.
Recommended
Industrial Automation and Control Nodes
In PLC I/O modules, pump controllers, and factory-automation nodes, the DSPIC33FJ128GP706AT-I/MR provides 40 MIPS headroom for control logic plus protocol handling, with the industrial -40C to +85C rating required on plant floors. The 128KB self-programmable flash supports field firmware updates through its ICSP interface or boot-loader firmware, and boundary scan capability aids production test on dense boards. GP peripherals cover UART-based Modbus, SPI-interfaced I/O expanders, and I2C sensors on one chip, reducing BOM count versus an MCU plus external DSP. Designers should budget the 3.0V-3.6V supply from a wide-input industrial regulator and place 0.1uF decoupling at every VDD pin; the tape-and-reel T suffix suits automated pick-and-place for volume panel assembly.
Recommended
Audio and Signal-Processing Front Ends
The DSPIC33FJ128GP706AT-I/MR executes audio-band filtering, level detection, and spectral analysis at 40 MIPS, making it practical for acoustic sensors, tone decoding, and low-channel-count audio conditioning where a dedicated DSP is overkill. Its dual 40-bit accumulators preserve dynamic range through long FIR convolutions in fixed-point arithmetic, and 128KB flash stores multiple coefficient banks for multi-mode products. The GP peripheral set's capture/compare resources timestamp external events while UART streams results to a host. Because the 3.0V-3.6V domain simplifies integration with 3.3V audio converters, the device can sit directly beside codec or amplifier circuitry; designers should verify ADC noise performance in the family datasheet against signal-chain dynamic-range targets, and consider an external low-noise analog front end where THD requirements are stringent.
Recommended
Embedded Systems Education and Prototyping
The DSPIC33FJ128GP706AT-I/MR is a strong platform for teaching 16-bit embedded control and DSP fundamentals because it is supported by Microchip's Explorer 16/32 Development Board via Processor Plug-In Modules, MPLAB X IDE, the XC16 compiler, and low-cost ICD debuggers. According to Microchip's product page, the Explorer 16/32 supports PIC24F, dsPIC, and PIC32 PIMs with PICtail Plus expansion, letting one board serve multiple lab exercises. Students progress from GPIO and timer labs to MAC-based DSP routines on the same silicon, and ICSP via PGD/PGC keeps programming hardware trivial. The main trade-off versus 32-bit teaching parts is a fixed-point programming model, which is arguably an advantage for learning DSP arithmetic and resource budgeting.
Recommended
Recommended Products Summary
Engineering reference data for DSPIC33FJ128GP706AT-I/MR — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | DSPIC33FJ128GP706AT-E/MR | DSPIC33FJ128GP706ATH/MR | DSPIC33FJ256GP706AT-I/MR | DSPIC33FJ64GP706AT-I/MR |
|---|---|---|---|---|---|
| Package | 64-VFQFN Exposed Pad (MR, 9x9 mm) | 64-VFQFN Exposed Pad (MR) - same | 64-PQCC (MR) - same | 64-VFQFN Exposed Pad (MR) - same | 64-VFQFN Exposed Pad (MR) - same |
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| Flash Memory | 128KB | 128KB | 128KB | 256KB | 64KB |
| Throughput | 40 MIPS (40 MHz) | 40 MHz | 40 MHz | 40 MIPS | 40 MIPS |
| Operating Temperature | -40C to +85C (Industrial) | -40C to +125C (Extended) | H grade (higher limit, per Microchip USA) | -40C to +85C (Industrial) | -40C to +85C (Industrial) |
| Core / DSP Features | 16-bit, single-cycle MAC, barrel shifter, boundary scan | Identical dsPIC33F core | Identical, barrel shifter + boundary scan | Identical dsPIC33F core | Identical dsPIC33F core |
Key Differentiators
- A-series silicon maturity (vs DSPIC33FJ128GP706T-I/MR)
- Extended temperature availability in the same footprint (vs DSPIC33FJ128GP706AT-E/MR)
- Balanced 128KB flash density (vs DSPIC33FJ64GP706AT-I/MR)
- Cost at volume (vs DSPIC33FJ128GP706ATH/MR)
Design Notes
Solder the 64-QFN exposed pad to a via-stitched ground island directly under the device. On no-lead packages the exposed pad is the primary ground return for the core and analog domains; relying on peripheral pins alone raises ground impedance and degrades ADC accuracy and EMC. Use a 9x9 mm landing pattern per the Microchip QFN footprint guideline with thermal vias (5x5 array, 0.3 mm drill, filled or tented) connecting to the internal ground plane.
Provide a regulated 3.0V-3.6V rail (nominal 3.3V) with at least 0.1uF ceramic decoupling at every VDD pin placed within 2 mm of each pin, plus 10uF bulk near the supply entry. Estimated: at 40 MIPS with typical GP peripheral loading, core current draw is in the tens-of-mA class per family datasheet typical figures; budget regulator headroom accordingly and confirm exact ICC from the current-versus-MIPS graphs in the family datasheet for your specific peripheral enablement.
Do not treat all '706' suffixes as identical: the target part is the A-series revision, which fixes errata present on the original dsPIC33FJ128GP706 silicon. When substituting DSPIC33FJ128GP706T-I/MR (non-A), cross-check the Microchip errata sheet for the affected peripheral (historically oscillator and ADC items on early dsPIC33FJ silicon). Also verify MCLR pull-up and PGD/PGC programming-pin isolation resistors per the programming specification before layout release, since ICSP sharing errors are the most common first-bring-up failure.
Compliance Information
RoHS compliance tagged on JLCPCB part listing C622852. No-lead QFN package per Vyrian terminal-form data. REACH, halogen-free, and conflict-minerals declarations not present in retrieved data - verify with Microchip environmental documentation.
