DSPIC33FJ64GP310AT-I/PF - 16-bit 40MIPS DSC 64KB Flash | Microchip
MPN: DSPIC33FJ64GP310AT-I/PF ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $7.9 | $7.90 |
| 10 | $7.11 | $71.10 |
| 100 | $6.32 | $632.00 |
| 500 | $5.69 | $2,845.00 |
| 1,000 | $5.06 | $5,060.00 |
DSPIC33FJ64GP310AT-I/PF Overview
A Digital Signal Controller combines the computational engine of a Digital Signal Processor (DSP) with the peripheral set and control architecture of a microcontroller (MCU). Within the semiconductor hierarchy, the dsPIC33F family sits between general-purpose MCUs such as the PIC24 and dedicated DSPs, offering single-cycle MAC, DSP multiply-accumulate, and hardware divide alongside standard embedded-control peripherals, making it a power-management IC-level cornerstone of mixed signal-control systems.
Key features include the 16-bit dsPIC core executing up to 40 MIPS, 64KB of self-programmable FLASH, 16KB of on-chip SRAM, and rich connectivity: I2C, SPI, UART/USART, IrDA, and LINbus interfaces. The GP (General Purpose) peripheral family integrates high-speed ADC, output compare and input capture channels suited for closed-loop control and signal acquisition.
Architecturally, the CMOS device pairs a pipelined CISC-style instruction stream with hardware DSP instructions, allowing C-compiled control loops and filtering kernels to coexist deterministically. The 40 MHz operating frequency with PLL options enables both high-throughput signal processing and low-power idle modes.
Typical applications include industrial motor control and digital power conversion, sensor acquisition and signal conditioning nodes, and communication/embedded control systems using LINbus or UART-based networks, where the DSP engine accelerates filtering while MCU peripherals handle protocol and I/O tasks.
A key design consideration is the 3.3V supply requirement with a -40C to +85C industrial operating range; decouple all VDD/VSS pairs and route the analog supply per the manufacturer application notes for ADC accuracy. Use MPLAB X IDE and supported programmers (e.g., ICD/REAL ICE class tools) for development.
This page synthesizes distributor pricing, drop-in family alternatives, and practical design notes not found in the manufacturer datasheet, with freshness signals as of 2026-09-27.
Drop-in alternatives for DSPIC33FJ64GP310AT-I/PF — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with DSPIC33FJ64GP310AT-I/PF (same form factor and footprint) — differing in Operating Temperature, Connectivity, Core, Packaging, Program Memory.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
DSPIC33FJ128GP310AT-I/PF
✅ Drop-In ⚠️ Specs Unverified✓ In Stock
$5.89 / Unit
View Datasheet →DSPIC33FJ256GP310AT-I/PF
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
DSPIC33FJ64GP310A-I/PF
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
DSPIC33FJ256GP510-I/PF
✅ Drop-In ⚠️ Specs Unverified✓ In Stock
$4.98 / Unit
View Datasheet →DSPIC33FJ256MC510T-I/PF
✅ Drop-In ⚠️ Specs Unverified✓ In Stock
$6.65 / Unit
View Datasheet →DSPIC33FJ64GP310AT-I/PF Maximum Ratings & Electrical Characteristics
| Core | 16-bit dsPIC RISC |
| Series | dsPIC33FJ64GP310A (dsPIC 33F) |
| Max MIPS / Frequency | 40 MIPS / 40 MHz |
| Program Memory | 64KB (64K x 8) FLASH |
| RAM | 16KB |
| Supply Voltage | 3.3 V |
| Connectivity | I2C, SPI, UART/USART, IrDA, LINbus |
| Package | 100-TQFP (14x14 mm), 0.5 mm pitch |
| Mounting Type | Surface Mount |
| Operating Temperature | -40C to +85C |
| Process Technology | CMOS |
| Product Type | Digital Signal Controller (DSC) |
| Packaging / Container | Tray (per TQFP PF packing) |
DSPIC33FJ64GP310AT-I/PF 100-tqfp (14x14 mm), 0.5 mm pitch Pin Configuration Guide
Pin configuration for DSPIC33FJ64GP310AT-I/PF (100-tqfp (14x14 mm), 0.5 mm pitch package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for DSPIC33FJ64GP310AT-I/PF.
Refer to the datasheet for full pin configuration.
Typical Applications
DSPIC33FJ64GP310AT-I/PF is suitable for 6 applications: Industrial Motor Control, Sensor Acquisition and Signal Conditioning, Industrial Communication Nodes (LINbus/UART), Audio and Voice Signal Processing, Embedded Control and Automation, Digital Power Conversion.
Industrial Motor Control
The DSPIC33FJ64GP310AT-I/PF fits closed-loop motor and power-conversion control because its 16-bit dsPIC33F core executes 40 MIPS with single-cycle MAC instructions, allowing FOC or PID loops plus filtering to run deterministically at kHz-rate sampling. Its fast ADC, input capture, and output-compare/PWM peripherals interface directly with current shunts, encoders, and gate-driver inputs. Placed as the system controller driving a three-phase inverter, the DSC performs current sampling, control-law computation, and PWM update in a single ISR. For advanced PWM features such as complementary outputs with dead-time insertion, Microchip's same-footprint MC-family parts are an upgrade path.
Recommended
Sensor Acquisition and Signal Conditioning
This DSC suits multi-channel sensor nodes because the 40 MIPS core with hardware DSP instructions performs FIR/IIR filtering, offset correction, and FFT-based analysis on-chip, while the integrated ADC, SPI, and I2C ports acquire data from temperature, pressure, and position sensors. The 64KB FLASH holds both the acquisition firmware and calibration tables, and 16KB RAM buffers sample streams. Data is streamed out via UART/USART or LINbus to a host. Because filtering executes in hardware MAC cycles rather than software emulation, CPU headroom remains for protocol handling, reducing the need for an external DSP or FPGA.
Recommended
Industrial Communication Nodes (LINbus/UART)
With native I2C, SPI, UART/USART, IrDA, and LINbus interfaces, the DSPIC33FJ64GP310AT-I/PF serves as a gateway or slave node in industrial and vehicular-adjacent networks. The 40 MIPS core executes LIN checksum handling, protocol state machines, and application logic concurrently without a separate communication coprocessor. The industrial -40C to +85C rating matches factory-floor conditions, and the 3.3V IO level mates with standard transceivers. FLASH self-programming allows field firmware updates over the UART/LIN link, extending service life of deployed nodes without hardware recalls.
Recommended
Audio and Voice Signal Processing
The GP-family DSC fits cost-sensitive audio processing where its single-cycle MAC and hardware modulo addressing implement sample-rate filters, AGC, and tone generation at audio rates. The 40 MIPS budget supports 16-bit processing at standard 8 kHz to 48 kHz sampling with margin, while UART/SPI links stream encoded audio to codecs. The 3.3V operation and 100-pin TQFP provide ample GPIO for user interface elements such as buttons, LEDs, and display buses. For products needing USB audio or higher dynamic range, migration within the dsPIC33F family preserves code investment.
Recommended
Embedded Control and Automation
As a general purpose DSC, the DSPIC33FJ64GP310AT-I/PF anchors automation controllers: the 100-pin TQFP exposes extensive GPIO for relays, optocoupled inputs, and HMI buses, while timers and input capture handle sequencing and event timing with microsecond resolution. The 64KB FLASH with self-write supports data logging and parameter storage strategies, and the industrial temperature rating suits unconditioned cabinets. Development uses MPLAB X with the Explorer 16/32 board via PIM modules, shortening prototyping. ICSP in-circuit programming enables production programming and field service through a single connector.
Recommended
Digital Power Conversion
The device applies to digitally controlled power supplies, battery chargers, and LED drivers where its fast ADC samples output voltage and current, and the 40 MIPS core closes voltage/current loops with compensator code executed each switching cycle. Output-compare channels generate gate-drive PWM with software-configurable frequency and duty update, while UART supports PMBus-like supervisory links to a host. 3.3V logic interfaces cleanly with gate-driver ICs and isolation components. Estimated: at 40 MIPS, a 10 kHz control loop consumes well under 20% of CPU budget, leaving capacity for housekeeping tasks and communication.
Recommended
Recommended Products Summary
Engineering reference data for DSPIC33FJ64GP310AT-I/PF — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | DSPIC33FJ128GP310AT-I/PF | DSPIC33FJ256GP310AT-I/PF | DSPIC33FJ64GP310A-I/PF | DSPIC33FJ256GP510-I/PF | DSPIC33FJ256MC510T-I/PF |
|---|---|---|---|---|---|---|
| Package | 100-TQFP (14x14 mm) | 100-TQFP (14x14 mm) - same | 100-TQFP (14x14 mm) - same | 100-TQFP (14x14 mm) - same | 100-TQFP (14x14 mm) - same | 100-TQFP (14x14 mm) - same |
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| Core / MIPS | 16-bit dsPIC, 40 MIPS | 16-bit dsPIC, 40 MIPS | 16-bit dsPIC, 40 MIPS | 16-bit dsPIC, 40 MIPS | 16-bit dsPIC, 40 MIPS | 16-bit dsPIC, 40 MIPS |
| FLASH | 64KB | 128KB | 256KB | 64KB | 256KB | 256KB |
| Supply Voltage | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V |
| Peripheral Family | GP (General Purpose) | GP | GP | GP | GP | MC (motor control PWM) |
| Operating Temperature | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C |
| Connectivity | I2C, SPI, UART/USART, IrDA, LINbus | Same set | Same set | Same set | Same set (verify instance count) | Same set (verify instance count) |
Key Differentiators
- Lowest FLASH in the GP310A 100-TQFP family (vs DSPIC33FJ128GP310AT-I/PF)
- GP peripheral family vs motor-control MC family (vs DSPIC33FJ256MC510T-I/PF)
- Cost efficiency vs top-of-family GP part (vs DSPIC33FJ256GP510-I/PF)
Design Notes
The 100-TQFP (14x14 mm, 0.5 mm pitch) requires careful decoupling: place a 100 nF ceramic capacitor at each VDD/VSS pair as close to the pins as possible, plus one bulk 10 uF capacitor per supply domain. Keep the oscillator traces short and guard them from PWM and communication lines. Verify the footprint against SnapEDA's verified model for this MPN before release to avoid land-pattern errors. Estimated: with 0.5 mm pitch, reflow profiles should follow the manufacturer's TQFP soldering specification to prevent lead bridging.
Configure unused I/O as outputs driven low or inputs with pull-ups to prevent floating-pin EMI and excess current. When migrating from DSPIC33FJ64GP310AT-I/PF to a 128KB or 256KB family variant, the linker scripts and device support files in MPLAB X must be updated, and configuration words re-checked - code compiled for the 64KB part links unchanged, but peripheral pin mappings shared with extra peripherals on larger dies should be re-verified against the target datasheet.
The device runs from a single 3.3V rail. Separate analog and digital supply domains with a ferrite bead and local decoupling to protect ADC accuracy from digital switching noise; refer to the Microchip 16-bit family analog design application notes for recommended filtering. Estimated: at 40 MIPS the core current is on the order of tens of mA per the family datasheet, so a 500 mA LDO or buck output comfortably powers one device plus IO loads.
Compliance Information
Compliance certificates for this exact MPN were not present in the verified web data; confirm via Microchip product page or distributor documentation before release.
