DSPIC33FJ64GP710A-E/PF - 16-bit DSC 40 MIPS 64KB Flash | Microchip
MPN: DSPIC33FJ64GP710A-E/PF ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $8.47 | $8.47 |
| 10 | $7.71 | $77.10 |
| 100 | $7.05 | $705.00 |
| 500 | $6.55 | $3,275.00 |
| 1,000 | $6.1 | $6,100.00 |
DSPIC33FJ64GP710A-E/PF Overview
A digital signal controller is a hybrid of a microcontroller (MCU) and a digital signal processor (DSP): it couples a 16-bit CPU with DSP-class multiply-accumulate (MAC) instructions, a barrel shifter, and dual operand fetch, while retaining the peripherals, interrupts, and ease of use of a classic microcontroller. In the power management hierarchy it sits between plain 8-bit MCUs and full 32-bit DSPs, making dsPIC33F devices the default choice for closed-loop control systems.
Key features include 16-bit fixed-point operation at up to 40 MIPS, 85 interrupt vectors, a rich analog suite, and five 16-bit timers. General purpose (GP) variants add audio-class peripherals: dual I2S CODEC interfaces, up to three UARTs, two CAN modules in some family members, up to 16-channel 10-bit ADC, output compare and input capture channels, and multiple PWM generators for motor control.
Architecturally, the dsPIC33F core uses a modified Harvard pipeline with 24-bit instruction words and a DSP engine offering single-cycle 40-bit MAC, division assist, and bit-reversed addressing for FFTs. Flash is self-programmable, and the A-version silicon (this part) incorporates Microchip errata fixes over the original dsPIC33FJ64GP710. Seamless migration options exist to PIC24 MCUs and dsPIC30F DSCs in similar packages.
Typical applications include switch-mode power supplies, digital lighting ballasts, sensorless PMSM and BLDC motor drives, audio processing and CODEC systems, and general industrial control where DSP math and MCU peripherals are both required.
Design consideration: run the device at 3.3V nominal (3.0-3.6V permitted for full 40 MIPS) and decouple VDDCORE/VCAP with the recommended low-ESR capacitor for core regulation stability.
This page synthesizes distributor pricing, drop-in family alternatives, and practical design notes not found in the manufacturer datasheet.
Drop-in alternatives for DSPIC33FJ64GP710A-E/PF — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with DSPIC33FJ64GP710A-E/PF (same form factor and footprint) — differing in Package, Operating Temperature, Program Memory Size, Core Architecture, DSP Engine.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
DSPIC33FJ64GP710A-I/PF
✅ Drop-In✓ In Stock
$4.78 / Unit
View Datasheet →DSPIC33FJ128GP710A-E/PF
✅ Drop-In ⚠️ Specs Unverified✓ In Stock
$6.25 / Unit
View Datasheet →DSPIC33FJ256GP710A-E/PF
✅ Drop-In ⚠️ Specs Unverified✓ In Stock
Contact for price
View Datasheet →DSPIC33FJ256GP510-I/PF
✅ Drop-In✓ In Stock
$4.98 / Unit
View Datasheet →DSPIC33FJ256GP510T-I/PT
✅ Drop-In✓ In Stock
$6.95 / Unit
View Datasheet →DSPIC33FJ64GP710A-E/PF Maximum Ratings & Electrical Characteristics
| Core | dsPIC33F 16-bit DSC |
| CPU Speed | Up to 40 MIPS |
| Program Memory | 64KB (64K x 8) Flash |
| RAM | 16KB |
| Supply Voltage | 3 V to 3.6 V |
| Operating Temperature | -40C to +125C |
| Package | 100-TQFP (14x14 mm) |
| Mounting Type | Surface Mount |
| Number of I/O | 85 |
| ADC Resolution | 10-bit |
| Timers | 5 x 16-bit |
| DSP Engine | Single-cycle MAC, barrel shifter |
| Communication Interfaces | UART, SPI, I2C, I2S |
| PWM Channels | Up to 8 output compare/PWM |
| Interrupt Vectors | 85 |
| Instruction Word | 24-bit |
| RoHS Status | Compliant |
| Temperature Grade | Extended (E) |
DSPIC33FJ64GP710A-E/PF Pin Configuration
| Pin 1 | MCLR — Master clear reset / programming voltage input |
| Pin 2 | AN0/VREF+/RB0 — Analog input 0 / ADC positive reference / PORTB bit 0 |
| Pin 3 | AN1/VREF-/RB1 — Analog input 1 / ADC negative reference / PORTB bit 1 |
| Pin 4 | AN2/SS1/RB2 — Analog input 2 / SPI slave select / PORTB bit 2 |
| Pin 5 | AN3/INDX/RB3 — Analog input 3 / QEI index / PORTB bit 3 |
| Pin 6 | AN4/QEA/IC7/RB4 — Analog input 4 / QEI phase A / capture 7 |
| Pin 7 | AN5/QEB/IC8/RB5 — Analog input 5 / QEI phase B / capture 8 |
| Pin 8 | AN6/OCFA/RC1 — Analog input 6 / output compare fault A |
| Pin 9 | AN7/RC0 — Analog input 7 / PORTC bit 0 |
| Pin 10 | AN8/CVREF/RC2 — Analog input 8 / comparator voltage reference |
| Pin 11 | AN9/RC3 — Analog input 9 / remappable peripheral pin |
| Pin 12 | AN10/RC4 — Analog input 10 / remappable peripheral pin |
| Pin 13 | VDD — Power supply (3.0-3.6V) |
| Pin 14 | VSS — Ground reference |
| Pin 15 | AN11/RC5 — Analog input 11 / remappable peripheral pin (parallel master write strobe) |
| Pin 16 | AN12/RC6 — Analog input 12 / remappable peripheral pin (parallel master read strobe) |
| Pin 17 | AN13/RC7 — Analog input 13 / remappable peripheral pin |
| Pin 18 | AN15/CF/RC8 — Analog input 15 / cycle-stolen function / fault input |
| Pin 19 | VDDCORE/VCAP — Core power / external regulator capacitor |
| Pin 20 | VSS — Ground reference |
| Pin 21 | AN16/RTCC/RG0 — Analog input 16 / RTCC / PORTG bit 0 |
| Pin 22 | AN17/RG1 — Analog input 17 / PORTG bit 1 |
| Pin 23 | SOSCI/T2CK/RG2 — Secondary oscillator input / timer 2 clock |
| Pin 24 | SOSCO/T1CK/RG3 — Secondary oscillator output / timer 1 clock |
| Pin 25 | RF12 — PORTF bit 12 / remappable peripheral pin |
| Pin 26 | RF13 — PORTF bit 13 / remappable peripheral pin |
| Pin 27 | VDD — Power supply |
| Pin 28 | VSS — Ground reference |
| Pin 29 | RF2 — PORTF bit 2 / remappable peripheral pin |
| Pin 30 | RF3 — PORTF bit 3 / remappable peripheral pin |
| Pin 31 | RF4 — PORTF bit 4 / remappable peripheral pin |
| Pin 32 | RF5 — PORTF bit 5 / remappable peripheral pin |
| Pin 33 | VDD — Power supply |
| Pin 34 | VSS — Ground reference |
| Pin 35 | RD8 — PORTD bit 8 / PMP write strobe |
| Pin 36 | RD9 — PORTD bit 9 / PMP read strobe |
| Pin 37 | RD10 — PORTD bit 10 / PMP chip select |
| Pin 38 | RD11 — PORTD bit 11 / PMP chip select |
| Pin 39 | RD12 — PORTD bit 12 / remappable peripheral pin |
| Pin 40 | RD13 — PORTD bit 13 / remappable peripheral pin |
| Pin 41 | RD0 — PORTD bit 0 / remappable peripheral pin |
| Pin 42 | RD1 — PORTD bit 1 / remappable peripheral pin |
| Pin 43 | RD2 — PORTD bit 2 / remappable peripheral pin |
| Pin 44 | RD3 — PORTD bit 3 / remappable peripheral pin |
| Pin 45 | RD4 — PORTD bit 4 / remappable peripheral pin |
| Pin 46 | VDD — Power supply |
| Pin 47 | VSS — Ground reference |
| Pin 48 | OSC1/CLKI — Primary oscillator input / external clock input |
| Pin 49 | OSC2/CLKO — Primary oscillator output / clock output |
| Pin 50 | RG8 — PORTG bit 8 / remappable peripheral pin |
| Pin 51 | RG7 — PORTG bit 7 / remappable peripheral pin |
| Pin 52 | RG6 — PORTG bit 6 / remappable peripheral pin |
| Pin 53 | VDD — Power supply |
| Pin 54 | VSS — Ground reference |
| Pin 55 | RD5 — PORTD bit 5 / remappable peripheral pin |
| Pin 56 | RD6 — PORTD bit 6 / remappable peripheral pin |
| Pin 57 | RD7 — PORTD bit 7 / remappable peripheral pin |
| Pin 58 | RF0 — PORTF bit 0 / remappable peripheral pin |
| Pin 59 | RF1 — PORTF bit 1 / remappable peripheral pin |
| Pin 60 | RD14 — PORTD bit 14 / remappable peripheral pin |
| Pin 61 | RD15 — PORTD bit 15 / remappable peripheral pin |
| Pin 62 | RE0/PMD0 — PORTE bit 0 / PMP data bus bit 0 |
| Pin 63 | RE1/PMD1 — PORTE bit 1 / PMP data bus bit 1 |
| Pin 64 | RE2/PMD2 — PORTE bit 2 / PMP data bus bit 2 |
| Pin 65 | RE3/PMD3 — PORTE bit 3 / PMP data bus bit 3 |
| Pin 66 | VDD — Power supply |
| Pin 67 | VSS — Ground reference |
| Pin 68 | RE4/PMD4 — PORTE bit 4 / PMP data bus bit 4 |
| Pin 69 | RE5/PMD5 — PORTE bit 5 / PMP data bus bit 5 |
| Pin 70 | RE6/PMD6 — PORTE bit 6 / PMP data bus bit 6 |
| Pin 71 | RE7/PMD7 — PORTE bit 7 / PMP data bus bit 7 |
| Pin 72 | RE8 — PORTE bit 8 / remappable peripheral pin |
| Pin 73 | RE9 — PORTE bit 9 / remappable peripheral pin |
| Pin 74 | RA14 — PORTA bit 14 / emulation clock |
| Pin 75 | RA15 — PORTA bit 15 / emulation data |
| Pin 76 | VDD — Power supply |
| Pin 77 | VSS — Ground reference |
| Pin 78 | SD1 — SPI1 data output (SDO1) |
| Pin 79 | SCK1 — SPI1 serial clock |
| Pin 80 | U2RX — UART2 receive |
| Pin 81 | U2TX — UART2 transmit |
| Pin 82 | U3RX — UART3 receive |
| Pin 83 | U3TX — UART3 transmit |
| Pin 84 | VDD — Power supply |
| Pin 85 | VSS — Ground reference |
| Pin 86 | RF12 — PORTF bit 12 / remappable peripheral pin |
| Pin 87 | RF13 — PORTF bit 13 / remappable peripheral pin |
| Pin 88 | AN14/RA0 — Analog input 14 / PORTA bit 0 |
| Pin 89 | RA1/TCK — PORTA bit 1 / JTAG test clock |
| Pin 90 | PGC1/RA2 — Programming clock 1 / PORTA bit 2 |
| Pin 91 | PGD1/RA3 — Programming data 1 / PORTA bit 3 |
| Pin 92 | RA4/TMS — PORTA bit 4 / JTAG test mode select |
| Pin 93 | RA5/TDI — PORTA bit 5 / JTAG test data in |
| Pin 94 | RA6 — PORTA bit 6 |
| Pin 95 | RA7 — PORTA bit 7 |
| Pin 96 | RA9/TDO — PORTA bit 9 / JTAG test data out |
| Pin 97 | RA10 — PORTA bit 10 |
| Pin 98 | AVDD — Analog power supply |
| Pin 99 | AVSS — Analog ground |
| Pin 100 | VSS — Ground reference |
Typical Applications
DSPIC33FJ64GP710A-E/PF is suitable for 6 applications: Digital Power Supplies and SMPS, BLDC and PMSM Motor Control, Audio Processing and CODEC Systems, Industrial Automation and Control Panels, Lighting Control and Ballasts, Portable and Embedded Instrumentation.
Digital Power Supplies and SMPS
The DSPIC33FJ64GP710A-E/PF fits digital power designs because its 40 MIPS core executes voltage- and current-loop compensators with single-cycle 40-bit MAC instructions, giving deterministic loop timing that software-compensated 32-bit MCUs struggle to match. High-resolution output compare/PWM channels generate converter gate drives, while the 10-bit ADC is synchronized to the PWM period for low-jitter sampling of inductor current and output voltage. Used as a full digital controller for LLC, buck, boost, or PFC stages, the DSC replaces analog compensation networks and enables adaptive mode switching. The -40C to +125C extended grade suits enclosed power supplies, and 64KB Flash is sufficient for the control firmware, soft-start, fault handling, and PMBus-style communication in most designs.
Recommended
BLDC and PMSM Motor Control
Sensorless motor control is a primary dsPIC33F use case, and the 64GP710A provides the full recipe: up to 8 PWM outputs for three-phase inverters, complementary or edge-aligned PWM modes with dead-time control, five 16-bit timers for rotor-position estimators, and a 10-bit ADC with simultaneous or sequential sampling of phase currents. The DSP engine performs Clarke/Park transforms and PI current loops in tens of cycles at 40 MIPS, allowing 16-bit fixed-point field-oriented control (FOC) loops above 10 kHz. The extended -40C to +125C rating covers industrial drives and sealed enclosures. With 85 I/O, the same chip can also host encoder interfaces, safety interlocks, and a UART or CAN link to the host controller without adding a second processor.
Recommended
Audio Processing and CODEC Systems
The General Purpose (GP) peripheral set on the dsPIC33FJ64GP710A includes I2S-capable serial interfaces, making it well suited to embedded audio: microphone arrays, Bluetooth speaker DSP front-ends, intercom and paging systems, and instrumentation audio filters. At 40 MIPS, the single-cycle MAC engine implements biquad filter chains, sample-rate converters, and audio effect blocks (EQ, AGC, echo) at 16-bit resolution with fixed-point arithmetic. The 16KB RAM buffers multiple audio channels without external memory. Analog audio conversion is handled by external CODECs connected over I2S/I2C, keeping the noise-sensitive conversion off-chip. The extended temperature grade and 100-pin TQFP with 85 I/O allow integration of user interfaces, LED indication, and communication links on a single controller.
Recommended
Industrial Automation and Control Panels
With 85 I/O pins, multiple UART/SPI/I2C ports, and robust interrupt structure, the DSPIC33FJ64GP710A-E/PF serves as a central controller in industrial automation: machine controllers, remote I/O modules, valve and actuator control, and condition-monitoring nodes. The 10-bit ADC samples pressure, temperature, and current sensors; timers and input captures decode flow or RPM pulses; and the DSP engine runs FFT-based vibration analysis for predictive maintenance. The -40C to +125C extended grade withstands panel temperatures near drives and heaters. Programming and field updates use the self-programmable Flash with a UART or ICSP bootloader. Debug is standardized through the PGC/PGD pins and Microchip MPLAB REAL ICE or ICD tooling, simplifying long-term maintainability of installed equipment.
Recommended
Lighting Control and Ballasts
Digital ballasts and high-intensity lighting controllers benefit from the dsPIC33F combination of PWM precision and DSP math. The 64GP710A generates phase-shifted or complementary PWM for resonant and buck LED drivers, dimming engines (0-10V, DALI over UART, or PWM), and lamp-life protection routines. The 10-bit ADC monitors input current, output current sharing across channels, and temperature sensors; the DSP engine executes power-factor correction and envelope tracking in real time at 40 MIPS. The extended -40C to +125C rating matches fixture environments where the controller sits near hot LED boards. 64KB Flash accommodates dimming curves, communication stacks, and safety cutoff logic, while 85 I/O integrates occupancy sensors, user controls, and network connectivity on one chip.
Recommended
Portable and Embedded Instrumentation
Battery-operated and benchtop instruments - dataloggers, handheld analyzers, sensor testers - use the DSPIC33FJ64GP710A-E/PF for its balance of compute and low power management. The 40 MIPS core accelerates FFT spectra, RMS calculations, and calibration math through hardware DSP instructions, while multiple low-power modes extend battery life between measurements. The 10-bit ADC plus external precision ADCs over SPI cover mixed-resolution sensing; UART, SPI, and I2C interfaces connect displays, SD cards, and USB-serial bridges. The 100-pin TQFP with 85 I/O drives keypad matrices, LCD segments, and status indicators directly. Self-programmable Flash supports field calibration storage and firmware updates, and MPLAB tooling with free XC16 compiler keeps development cost near zero.
Recommended
Recommended Products Summary
Engineering reference data for DSPIC33FJ64GP710A-E/PF — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | DSPIC33FJ64GP710A-I/PF | DSPIC33FJ256GP710A-E/PF | DSPIC33FJ256GP510-I/PF |
|---|---|---|---|---|
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| Package | 100-TQFP (14x14 mm) | 100-TQFP (14x14 mm) - same | 100-TQFP (14x14 mm) - same | 100-TQFP (14x14 mm) - same |
| Flash Memory | 64KB | 64KB | 256KB | 256KB |
| CPU Speed | Up to 40 MIPS | Up to 40 MIPS | Up to 40 MIPS | Up to 40 MIPS |
| RAM | 16KB | 16KB | 16KB | 30KB |
| Supply Voltage | 3 V to 3.6 V | 3 V to 3.6 V | 3 V to 3.6 V | 3 V to 3.6 V |
| Operating Temperature | -40C to +125C (E grade) | -40C to +85C (I grade) | -40C to +125C (E grade) | -40C to +85C (I grade) |
Key Differentiators
- Extended -40C to +125C operation at standard price point (vs DSPIC33FJ64GP710A-I/PF)
- Deterministic DSP math for control loops (vs Generic 32-bit Cortex-M0+ MCUs)
- Migration path within the same footprint (vs DSPIC33FJ64GP710A-E/PF (this part))
Design Notes
The dsPIC33F core is regulated on-chip: VDDCORE/VCAP (pin 19) must be tied to a low-ESR ceramic capacitor to ground as specified in the Microchip datasheet (typically 10uF plus 0.1uF). Omitting or mis-sizing this capacitor causes core brownouts and sporadic resets. Distribute multiple VDD/VSS pairs across the 100-pin TQFP and place a 0.1uF ceramic capacitor within 2 mm of each pair, plus one bulk 10uF per power domain. Separate AVDD/AVSS (pins 98-99) with an RC or ferrite filter for clean ADC references.
For the 14x14 mm TQFP-100, route the PGC/PGD programming pins (PGC1/RA2, PGD1/RA3) to an ICSP header even in production boards - field firmware updates and debugging depend on it. Keep the primary oscillator (OSC1/OSC2) traces short and guard them with ground; if using EC mode with an external clock, the internal PLL can generate 40 MIPS (7.37 MHz FRC or external clock x PLL). PMP data bus (RE0-RE7) and strobe pins should be length-matched if driving external parallel peripherals above 8 MHz PMP clocks.
Use the 'A'-version errata sheet: early non-A dsPIC33FJ64GP710 silicon had documented ADC and oscillator errata; this A-version fixes them but requires configuration bit review when porting code. Watch MCLR during programming: it doubles as high-voltage programming input (about 9V for HV programming in some family members) - protect downstream circuitry. Finally, all 40 MIPS operation requires VDD within 3.0-3.6V; at reduced VDD the Fmax derates per the Microchip operating range table.
Compliance Information
RoHS compliance and lead-free status per LCSC and JLCPCB distributor listings. REACH, halogen-free and conflict minerals status not stated in provided data.
