DSPIC33FJ64GP802-I/SP - 16-bit DSC 40MIPS 64KB Flash | Microchip
MPN: DSPIC33FJ64GP802-I/SP ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $6.62 | $6.62 |
| 10 | $6.02 | $60.20 |
| 25 | $5.54 | $138.50 |
| 100 | $4.92 | $492.00 |
| 1,000 | $4.05 | $4,050.00 |
DSPIC33FJ64GP802-I/SP Overview
A Digital Signal Controller combines the computational architecture of a Digital Signal Processor with the peripheral set and ease of use of a microcontroller. Within the power management hierarchy of embedded systems, the DSC sits between a general-purpose MCU and a dedicated DSP, making it the natural choice when a design needs both control-flow code (state machines, communication stacks) and math-heavy loops (PID controllers, digital filters) on a single chip. The dsPIC33F family from Microchip Technology is one of the most widely adopted 16-bit DSC platforms in industrial electronics.
Key features of the DSPIC33FJ64GP802 include a modified Harvard architecture executing one instruction per cycle at 40 MIPS, eight channels of DMA for moving ADC results and UART data without CPU intervention, seven timers, three serial I/O ports (UART, SPI, I2C), and a 10-bit, up to 500 ksps ADC with multiple simultaneous-sampling capable inputs. A hardware 17x17 multiplier, 40-bit barrel shifter, and DSP multiply-accumulate instructions accelerate filter and control algorithms that would stall a conventional 8-bit MCU.
The device operates from a 3.0 V to 3.6 V supply and is supported by Microchip's free XC16 compiler, MPLAB X IDE, and the Explorer 16/32 Development Board via a Plug-In Module, giving engineers a complete low-cost toolchain from day one. In-circuit serial programming (ICSP) and debugging use any PGECx/PGEDx pin pair.
Typical applications include motor control (BLDC/PMSM FOC), digital power conversion, industrial sensing and signal conditioning, audio processing, and precision instrumentation where digital filters and fast control loops are required.
Design consideration: pin 28 requires a low-ESR VCAP/VDDCORE capacitor per the datasheet, and all VDD/VSS pairs must be decoupled with 0.1 uF ceramics placed at the pins; the through-hole SPDIP package simplifies prototyping but limits analog performance versus the SOIC variant.
This page synthesizes drop-in alternatives, parametric comparisons, and practical design notes not found in the manufacturer datasheet, with pricing as of 2026-09-27.
Drop-in alternatives for DSPIC33FJ64GP802-I/SP — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with DSPIC33FJ64GP802-I/SP (same form factor and footprint) — differing in Package, DMA Channels, Operating Temperature, Core Architecture, RoHS Status.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
DSPIC33FJ64GP202-I/SP
✅ Drop-In📋 Reference alternative (not in catalog)
DSPIC33FJ32GP302-I/SP
✅ Drop-In✓ In Stock
$3.7 / Unit
View Datasheet →DSPIC33FJ32MC202-I/SP
✅ Drop-In ⚠️ Specs Unverified✓ In Stock
$3.25 / Unit
View Datasheet →DSPIC33FJ16GS502-I/SP
✅ Drop-In ⚠️ Specs Unverified✓ In Stock
$3.18 / Unit
View Datasheet →DSPIC33FJ64GP802-I/SP Maximum Ratings & Electrical Characteristics
| Core Architecture | 16-bit modified Harvard DSC |
| Maximum Clock Speed | 40 MHz (40 MIPS) |
| Flash Program Memory | 64 KB |
| SRAM | 16 KB |
| Supply Voltage | 3 V to 3.6 V |
| DMA Channels | 8 |
| Timers | 7 |
| Serial Interfaces | 3 (UART, SPI, I2C) |
| ADC Resolution | 10-bit |
| ADC Throughput | up to 500 ksps |
| I/O Ports | 21 |
| DSP Engine | 17x17 hardware multiplier, 40-bit barrel shifter, MAC instructions |
| Operating Temperature | -40C to +85C |
| Package | 28-pin SPDIP (SP) |
| Mounting Type | Through-Hole |
| Programming/Debug | ICSP via PGECx/PGEDx pairs (ICD 3, PICkit 3/4, NSDSP) |
| Lifecycle Status | Active |
DSPIC33FJ64GP802-I/SP Pin Configuration
| Pin 1 | MCLR — Master clear reset input / programming voltage |
| Pin 2 | AN0/CN2/RB0 — Analog input 0 / digital I/O |
| Pin 3 | AN1/CN3/RB1 — Analog input 1 / digital I/O |
| Pin 4 | AN2/SS1/CN4/RB2 — Analog input 2 / SPI slave select / digital I/O |
| Pin 5 | AN3/INDX/CN5/RB3 — Analog input 3 / QEI index / digital I/O |
| Pin 6 | AN4/QEA/IC7/CN6/RB4 — Analog input 4 / QEI phase A / capture 7 / digital I/O |
| Pin 7 | VDD — Positive supply (3.0-3.6 V) |
| Pin 8 | VSS — Ground reference |
| Pin 9 | OSC1/CLKI/CN7/RA2 — Oscillator input / external clock |
| Pin 10 | OSC2/CLKO/RC15 — Oscillator output / clock output / digital I/O |
| Pin 11 | SDA1/EMUD1/RP1/CN1/RF1 — I2C data 1 / remappable peripheral pin RP1 / digital I/O |
| Pin 12 | SCL1/EMUC1/RP0/CN0/RF0 — I2C clock 1 / remappable peripheral pin RP0 / digital I/O |
| Pin 13 | VSS — Ground reference |
| Pin 14 | VDD — Positive supply (3.0-3.6 V) |
| Pin 15 | IC1/EMUD3/RP2/CN14/RF2 — Input capture 1 / remappable peripheral pin RP2 / digital I/O |
| Pin 16 | U1RX/EMUC3/RP3/CN13/RF3 — UART1 receive / remappable peripheral pin RP3 / digital I/O |
| Pin 17 | U1TX/SDO1/RP6/RF6 — UART1 transmit / SPI1 data out / remappable RP6 / digital I/O |
| Pin 18 | IC2/RP7/RF7 — Input capture 2 / remappable RP7 / digital I/O |
| Pin 19 | IC3/RP8/RF8 — Input capture 3 / remappable RP8 / digital I/O |
| Pin 20 | RB5/PGD1/EMUD/IC4/RP9/RF9 — Digital I/O / primary ICSP data / capture 4 / remappable RP9 |
| Pin 21 | RP10/U1CTS/RF10 — Remappable RP10 / UART1 clear-to-send / digital I/O |
| Pin 22 | PGD3/RP11/RF11 — ICSP data pair 3 / remappable RP11 / digital I/O |
| Pin 23 | PGEC2/RP12/RF12 — ICSP clock pair 2 / remappable RP12 / digital I/O |
| Pin 24 | PGD2/RP13/RF13 — ICSP data pair 2 / remappable RP13 / digital I/O |
| Pin 25 | AVSS — Analog ground reference |
| Pin 26 | AVDD — Analog positive supply |
| Pin 27 | AN9/RP15/RB15 — Analog input 9 / remappable RP15 / digital I/O |
| Pin 28 | VCAP/VDDCORE — Internal core regulator output capacitor connection |
Typical Applications
DSPIC33FJ64GP802-I/SP is suitable for 6 applications: Motor Control (BLDC/PMSM FOC), Digital Power Conversion, Industrial Sensing and Signal Conditioning, Audio Processing, Precision Instrumentation, Embedded Education and Prototyping.
Motor Control (BLDC/PMSM FOC)
The DSPIC33FJ64GP802-I/SP fits motor control because its 40 MIPS core, 17x17 hardware multiplier, and DSP MAC instructions execute field-oriented control loops at 10-20 kHz PWM frequencies with ample cycle margin. The 10-bit 500 ksps ADC samples phase currents, and 8 DMA channels stream results into RAM without CPU intervention, leaving the full core for the control algorithm. In a typical topology, complementary PWM drives a three-phase inverter gate-driver stage while the ADC synchronizes current sampling to the PWM center. The through-hole SPDIP package makes it a favorite for prototyping inverter boards before committing to a surface-mount production layout.
Recommended
Digital Power Conversion
For digitally controlled AC-DC and DC-DC converters, the DSPIC33FJ64GP802-I/SP offers the 40 MIPS throughput and hardware multiply needed for voltage-mode or average-current-mode control loops executed every switching cycle. Its 7-timer bank generates multiple PWM phases, and the DMA engine keeps ADC sampling of output voltage and inductor current deterministic. Compared with an analog controller, firmware-based control allows adaptive compensation and soft-start profiles. Design consideration: the 10-bit ADC resolution constrains loop precision versus 12-bit GS-family parts, so for high-precision telecom rectifiers consider the DSPIC33FJ16GS502-I/SP, which is pin-compatible in the same 28-pin SPDIP footprint for easy evaluation-board reuse.
Recommended
Industrial Sensing and Signal Conditioning
The GP802's multi-channel 10-bit ADC with simultaneous sampling capability, VREF+ and VREF- pins, and 500 ksps throughput makes it a compact front end for industrial transmitters and sensor conditioners. DSP instructions implement IIR notch filters and RMS computations directly on-chip, eliminating an external signal-processing device. The 3.3 V supply matches modern analog front-end ICs, and the 21 I/O lines drive 4-20 mA output stages or HART modems through UART. The SPDIP through-hole package suits DIN-rail prototype carriers and low-volume industrial builds where hand rework and socketed field replacement are more valuable than board density.
Recommended
Audio Processing
The GP (General Purpose) peripheral set of the DSPIC33FJ64GP802-I/SP includes audio-oriented serial ports and DMA that support I2S-style streaming and real-time effects at 40 MIPS. The 64 KB Flash holds fixed-point filter banks, while the 16 KB SRAM buffers audio blocks transferred by the 8 DMA channels. Typical uses include active crossovers, noise cancellation prototypes, and speech-band processing in educational DSP kits. For a production pipeline, place the DSC between an audio codec and a power amplifier stage; the 3.3 V rail simplifies shared supplies with codec ICs, and the SPDIP package enables fast iteration of filter coefficient changes on a solderless development carrier.
Recommended
Precision Instrumentation
Bench instruments, data loggers, and handheld meters benefit from the DSPIC33FJ64GP802-I/SP's combination of a 10-bit ADC, three serial ports for PC and display connectivity, and DSP math for calibration and linearization. The 64 KB Flash stores lookup tables and self-test firmware, while ICSP debugging through any PGECx/PGEDx pair speeds firmware iteration on the instrument PCBA. The -40C to +85C industrial rating covers most lab and field environments. The through-hole 28-pin SPDIP format is especially convenient for instrument prototypes that use wire-wrap or socketed carrier boards during the bring-up and calibration phase.
Recommended
Embedded Education and Prototyping
The DSPIC33FJ64GP802-I/SP is a staple of university DSP and embedded-systems courses because it runs on the Microchip Explorer 16/32 Development Board via a Plug-In Module, is programmable with the free XC16 compiler and MPLAB X IDE, and its 2.54 mm SPDIP package survives repeated insertion into breadboards and sockets. Students implement FIR filters, PID loops, and FFTs using the hardware MAC with textbook efficiency. The active lifecycle status guarantees long-term availability for course kits. XAIPART stocks related PIC18 28-pin SPDIP parts such as PIC18F2520-I/SP, enabling progressive 8-bit to 16-bit lab tracks on shared tooling.
Recommended
Recommended Products Summary
Engineering reference data for DSPIC33FJ64GP802-I/SP — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | DSPIC33FJ64GP202-I/SP | DSPIC33FJ32GP302-I/SP | DSPIC33FJ64GP202T-I/SO | DSPIC33FJ32MC202-I/SP | DSPIC33FJ16GS502-I/SP |
|---|---|---|---|---|---|---|
| Package | 28-SPDIP | 28-SPDIP - same | 28-SPDIP - same | 28-SOIC | 28-SPDIP - same | 28-SPDIP - same |
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| Core / MIPS | 16-bit, 40 MIPS | 16-bit, 40 MIPS | 16-bit, 40 MIPS | 16-bit, 40 MIPS | 16-bit, 40 MIPS | 16-bit, 40 MIPS |
| Flash | 64 KB | 64 KB | 32 KB | 64 KB | 32 KB | 16 KB |
| Supply Voltage | 3.0-3.6 V | 3.0-3.6 V | 3.0-3.6 V | 3.0-3.6 V | 3.0-3.6 V | 3.0-3.6 V |
| Peripheral Orientation | General purpose + audio/analog | General purpose (reduced set) | General purpose | General purpose (reduced set) | Motor control | Digital power (SMPS) |
| Operating Temperature | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C |
Key Differentiators
- Twice the program memory of 32 KB family members (vs DSPIC33FJ32GP302-I/SP)
- Full general-purpose peripheral set with audio/analog orientation (vs DSPIC33FJ32MC202-I/SP)
- Through-hole SPDIP for prototyping and education (vs DSPIC33FJ64GP202T-I/SO)
Design Notes
The internal regulator derives the 1.8 V core from the 3.3 V VDD rail through the VCAP pin (pin 28). Fit a low-ESR ceramic capacitor (datasheet value on the order of 10 uF) directly at pin 28 to ground; omitting it or using a high-ESR part causes brown-out resets and erratic operation. Decouple every VDD pin (7, 14) and AVDD (26) with 0.1 uF ceramics placed within a few millimeters of the pin, and tie AVSS (25) to a quiet analog ground.
Even on a through-hole prototype, keep the analog front end (AN0-AN4 on pins 2-6, VREF pins) away from the oscillator loop on pins 9-10 and from PWM switching nodes. Use a crystal with load capacitors matched to the datasheet oscillator section, or rely on the internal FRC oscillator with PLL for 40 MIPS operation without external components. Route PGECx/PGEDx debug pairs to a 5-pin ICSP header on all boards - retrofitting one later on a 28-pin DIP socket is possible but error-prone because any PGEC/PGED pair must be used together.
Two frequent dsPIC33F mistakes: first, the PPS (Peripheral Pin Select) system must be unlocked and configured in code before UART, SPI, or PWM appear on RP pins - peripherals do not appear at fixed pins by default. Second, flash write/erase operations require the core to run from RAM or be halted; executing flash writes from flash itself stalls or faults the CPU. Consult the Microchip family reference manual section on flash programming, and verify config-bit settings (watchdog, oscillator, brown-out) before first programming.
Compliance Information
Lead-free/RoHS per Microchip current product page and the -I/SP ordering code. Digchip listing references a lead-free package note for the family. REACH/halogen status not stated in provided data.
