DSPIC33FJ64MC706A-E/MR - 16-bit 40MIPS DSC 64KB | Microchip
MPN: DSPIC33FJ64MC706A-E/MR ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $7.42 | $7.42 |
| 10 | $6.75 | $67.50 |
| 100 | $6.1 | $610.00 |
| 500 | $5.65 | $2,825.00 |
| 1,000 | $5.2 | $5,200.00 |
DSPIC33FJ64MC706A-E/MR Overview
A digital signal controller combines the deterministic interrupt response and peripheral set of a microcontroller with the multiply-accumulate computational throughput of a DSP. In the power-management hierarchy of embedded systems, a DSC sits between a general-purpose MCU and a dedicated DSP: it executes real-time control loops, such as field-oriented control of motors, while managing communication, sensing, and system supervision on the same silicon.
Key features include the 16-bit dsPIC33F core with DSP instruction extensions, an on-chip CAN 2.0B controller for industrial networking, motor-control PWM peripherals capable of complementary outputs with dead-time insertion, and advanced analog integration for sensing. The dsPIC33FJ64MC706A family is explicitly optimized for motor control applications by Microchip, covering brushless DC, single- and 3-phase induction, and switched reluctance motor architectures.
Technically, the device executes up to 40 million instructions per second at 3.0V to 3.6V operation, with a 24-bit instruction word architecture. Seamless migration paths exist to PIC24 MCU and dsPIC30F DSC devices in similar packages, protecting software investment. The extended -40C to +125C E-temperature suffix suits industrial enclosures, traction cabinets, and under-hood-adjacent electronics where ambient temperatures exceed commercial ratings.
Typical applications include brushless DC motor drives, 3-phase induction motor inverters, uninterruptible power supplies (UPS), switched reluctance motor controllers, and power-factor-correction stages where the PWM engine, ADC, and CAN bus operate in a coordinated real-time loop.
A key design consideration is supply integrity: the QFN exposed pad must be soldered to a solid ground plane, and decoupling capacitors placed directly at each VDD/VSS pair to support the 40 MHz switching currents during simultaneous PWM edge transitions.
This page synthesizes distributor pricing, drop-in same-package alternatives, pinout guidance, and practical design notes not consolidated in the manufacturer datasheet.
Drop-in alternatives for DSPIC33FJ64MC706A-E/MR — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with DSPIC33FJ64MC706A-E/MR (same form factor and footprint) — differing in Core Architecture, Package, DMA Channels, Motor Control PWM, Operating Temperature.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
DSPIC33FJ128MC706A-E/MR
✅ Drop-In ⚠️ Specs Unverified✓ In Stock
$7.6 / Unit
View Datasheet →DSPIC33FJ256MC706A-E/MR
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
DSPIC33FJ32MC706A-E/MR
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
DSPIC33FJ64MC706AT-E/MR
✅ Drop-In📋 Reference alternative (not in catalog)
DSPIC33FJ64MC706A-E/PT
✅ Drop-In✓ In Stock
$5.85 / Unit
View Datasheet →DSPIC33FJ64MC706A-E/MR Maximum Ratings & Electrical Characteristics
| Core Architecture | 16-bit dsPIC33F DSC |
| Maximum Clock Frequency | 40 MHz |
| Performance | 40 MIPS |
| Program Memory (Flash) | 64 KB |
| RAM | 16,384 words |
| Instruction Width | 24 bit |
| Package | 64-QFN with exposed pad (MR) |
| Operating Temperature Range | -40C to +125C |
| Communication Interfaces | CAN 2.0B, UART, SPI, I2C |
| Motor Control PWM | Yes (complementary PWM with dead-time control) |
| Mounting Type | Surface Mount |
| Container / Packaging | Tube |
| Category | Digital Signal Processors & Controllers (DSP, DSC) |
| Family Specialization | Motor Control and Advanced Analog |
DSPIC33FJ64MC706A-E/MR Pin Configuration
| Pin 1 | MCLR — Master clear reset input, active low |
| Pin 2 | AN0/VREF+/CN2/RB0 — Analog input 0 / positive voltage reference |
| Pin 3 | AN1/VREF-/CN3/RB1 — Analog input 1 / negative voltage reference |
| Pin 4 | AN2/SS1/CN4/RB2 — Analog input 2 / SPI1 slave select |
| Pin 5 | AN3/INDX/CN5/RB3 — Analog input 3 / QEI index input |
| Pin 6 | AN4/QEA/IC7/CN6/RB4 — Analog input 4 / QEI phase A / input capture 7 |
| Pin 7 | AN5/QEB/IC8/CN7/RB5 — Analog input 5 / QEI phase B / input capture 8 |
| Pin 8 | VSS — Ground reference |
| Pin 9 | OSC1/CLKI/CN30/RA2 — Crystal oscillator input / external clock input |
| Pin 10 | OSC2/CLKO/ECOUT/CN29/RA3 — Crystal oscillator output / clock output |
| Pin 11 | VDD — Positive supply (3.0V-3.6V) |
| Pin 12 | VSS — Ground reference |
| Pin 13 | SOSCI/CN1/RB6 — Secondary oscillator input / change notification |
| Pin 14 | SOSCO/T1CK/CN0/RB7 — Secondary oscillator output / Timer1 clock |
| Pin 15 | CN8/RC7/U1CTS — Change notification / UART1 CTS |
| Pin 16 | U1TX/SDO1/RC6 — UART1 transmit / SPI1 data out |
| Pin 17 | U1RX/SDI1/RC5 — UART1 receive / SPI1 data in |
| Pin 18 | SCK1/RC4 — SPI1 serial clock |
| Pin 19 | CN5/RC3 — Port C I/O / change notification |
| Pin 20 | T2CK/RC2 — Timer2 external clock input |
| Pin 21 | T1CK/IC1/RC1 — Timer1 clock / input capture 1 |
| Pin 22 | OC1/RC0 — Output compare 1 output |
| Pin 23 | PWM1L1/RE0 — Motor PWM 1 low output, channel 1 |
| Pin 24 | PWM1H1/RE1 — Motor PWM 1 high output, channel 1 |
| Pin 25 | PWM1L2/RE2 — Motor PWM 1 low output, channel 2 |
| Pin 26 | PWM1H2/RE3 — Motor PWM 1 high output, channel 2 |
| Pin 27 | PWM1L3/RE4 — Motor PWM 1 low output, channel 3 |
| Pin 28 | PWM1H3/RE5 — Motor PWM 1 high output, channel 3 |
| Pin 29 | FLT1/RE6 — PWM fault input 1 |
| Pin 30 | PWM1L4/RE7 — Motor PWM 1 low output, channel 4 |
| Pin 31 | PWM1H4/RF0 — Motor PWM 1 high output, channel 4 |
| Pin 32 | RF1 — Port F I/O |
| Pin 33 | C1TX/RF2 — CAN1 transmit output |
| Pin 34 | C1RX/RF3 — CAN1 receive input |
| Pin 35 | RF4 — Port F I/O |
| Pin 36 | RF5 — Port F I/O |
| Pin 37 | SCL1/RF6 — I2C1 serial clock |
| Pin 38 | SDA1/RF7 — I2C1 serial data |
| Pin 39 | RG0/U2TX — UART2 transmit |
| Pin 40 | RG1/U2RX — UART2 receive |
| Pin 41 | AN6/RG2 — Analog input 6 / port G I/O |
| Pin 42 | AN7/RG3 — Analog input 7 / port G I/O |
| Pin 43 | VDD — Positive supply |
| Pin 44 | VSS — Ground reference |
| Pin 45 | AN8/RB8 — Analog input 8 / port B I/O |
| Pin 46 | AN9/RB9 — Analog input 9 / port B I/O |
| Pin 47 | AN10/RB10 — Analog input 10 / port B I/O |
| Pin 48 | AN11/RB11 — Analog input 11 / port B I/O |
| Pin 49 | VDD — Positive supply |
| Pin 50 | VSS — Ground reference |
| Pin 51 | AN12/RB12 — Analog input 12 / port B I/O |
| Pin 52 | AN13/RB13 — Analog input 13 / port B I/O |
| Pin 53 | AN14/RB14 — Analog input 14 / port B I/O |
| Pin 54 | AN15/CVREF/RB15 — Analog input 15 / comparator voltage reference |
| Pin 55 | AVDD — Analog supply (3.0V-3.6V) |
| Pin 56 | AVSS — Analog ground |
| Pin 57 | RD0/OC3 — Output compare 3 / port D I/O |
| Pin 58 | RD1/OC4 — Output compare 4 / port D I/O |
| Pin 59 | RD2/IC3 — Input capture 3 / port D I/O |
| Pin 60 | RD3/IC4 — Input capture 4 / port D I/O |
| Pin 61 | RD4 — Port D I/O |
| Pin 62 | RD5/IC2 — Input capture 2 / port D I/O |
| Pin 63 | RD6/OC2 — Output compare 2 / port D I/O |
| Pin 64 | EP/VSS — Exposed pad - connect to ground plane (thermal and electrical ground) |
Typical Applications
DSPIC33FJ64MC706A-E/MR is suitable for 6 applications: Brushless DC (BLDC) Motor Drives, 3-Phase Induction Motor Inverters, Uninterruptible Power Supplies (UPS), Switched Reluctance Motor (SRM) Controllers, Industrial Networked Nodes with CAN, Embedded Motion and Robotics Control.
Brushless DC (BLDC) Motor Drives
The DSPIC33FJ64MC706A-E/MR is purpose-built for BLDC control: its motor-control PWM peripheral generates three complementary output pairs with hardware dead-time insertion, directly driving a 3-phase inverter gate-driver stage. The 40 MIPS core executes sensorless observers or Hall-based commutation with cycle time to spare, while synchronized ADC sampling captures phase currents at PWM centers to avoid switching noise. On-chip CAN 2.0B links the drive into industrial networks without stealing CPU cycles from the control loop. The -40C to +125C E-temperature rating suits sealed drive housings where ambient near the power stage regularly exceeds +85C. The 64-QFN exposed pad provides a low-inductance ground reference that keeps PWM edge ringing out of ADC measurements.
Recommended
3-Phase Induction Motor Inverters
For single- and 3-phase induction motor control, the DSC runs V/Hz or field-oriented control algorithms on its DSP-enhanced 16-bit core at 40 MIPS, while dedicated PWM hardware produces the six switching signals with programmable dead time. Synchronized analog-to-digital conversion samples DC-bus voltage and phase currents each PWM cycle for closed-loop flux and torque estimation. The 64 KB flash accommodates a complete control stack including start-up sequencing, protection routines, and a CAN or UART communication task. Extended -40C to +125C operation permits mounting inside inverter cabinets near heatsinks. The QFN exposed pad solders to the PCB ground plane, improving both thermal dissipation under sustained 40 MHz operation and electromagnetic compatibility of high-edge-rate PWM signals.
Recommended
Uninterruptible Power Supplies (UPS)
UPS inverters demand precisely phase-shifted PWM generation, fast fault shutdown, and continuous sensing of output voltage and battery current - all tasks the dsPIC33FJ64MC706A architecture addresses. The motor-control PWM module generates sinusoidal carrier-based modulation for the inverter bridge, with hardware dead-time protecting against shoot-through, while ADC channels synchronized to the PWM period sample the output waveform for closed-loop regulation at switching frequency. The 40 MIPS core simultaneously executes protection logic, battery-charging management, and host communication over UART or CAN. Microchip explicitly lists UPS among the target applications of this family, and the extended -40C to +125C range covers equipment installed in unconditioned electrical rooms where summer ambient approaches the upper ratings.
Recommended
Switched Reluctance Motor (SRM) Controllers
Switched reluctance drives require asymmetric, independently timed phase excitations - a control pattern the dsPIC33FJ64MC706A supports through its flexible motor-control PWM with per-output override control. The 40 MIPS core handles torque-ripple-minimization algorithms and rotor-position estimation from phase inductance signatures sampled by the synchronized ADC, eliminating discrete position sensors. The DSP multiply-accumulate instructions accelerate the observer mathematics that a standard 16-bit MCU would struggle to close within a 10-20 kHz control period. The -40C to +125C E-grade rating matches the hot, vibration-prone environments (pumps, fans, compressors) where SRM drives excel. The 64-QFN footprint with exposed pad keeps ground impedance low across high di/dt phase-switching events, protecting analog measurement integrity.
Recommended
Industrial Networked Nodes with CAN
The integrated CAN 2.0B controller makes the DSPIC33FJ64MC706A-E/MR a complete CAN node on one chip: hardware message framing, acceptance filtering, and multiple transmit/receive buffers operate without core intervention, leaving the 40 MIPS DSP core free for application tasks such as sensor fusion or local closed-loop control. Pairing motor-control PWM with CAN lets one device serve as both a drive controller and a fieldbus slave in conveyors, HVAC blowers, and pumping skids, removing a second communication processor. The UART, SPI, and I2C peripherals connect auxiliary sensors and human-interface hardware. The -40C to +125C extended rating and 64-QFN exposed-pad grounding support deployment in outdoor cabinets and near switching power stages typical of industrial installations.
Recommended
Embedded Motion and Robotics Control
Robotics axes need coordinated multi-motor control, encoder feedback processing, and deterministic real-time response - the dsPIC33FJ64MC706A provides the quadrature-encoder interface inputs, motor-control PWM, and 40 MIPS interrupt-driven core to close current and velocity loops on multiple axes from one device. The DSP MAC instructions execute PI/PID and field-orientation mathematics efficiently, while CAN interconnects axes in distributed servo topologies. The 64 KB flash holds per-axis profiles, homing logic, and safety interlocks; designs needing trajectory planning tables can drop in the pin-compatible DSPIC33FJ128MC706A-E/MR without PCB changes. Extended -40C to +125C operation tolerates drive-mounted placement near power electronics, and the QFN thermal pad sustains continuous full-speed operation without external heatsinking in typical ambient conditions.
Recommended
Recommended Products Summary
Engineering reference data for DSPIC33FJ64MC706A-E/MR — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | DSPIC33FJ128MC706A-E/MR | DSPIC33FJ32MC706A-E/MR | DSPIC33FJ64MC706AT-E/MR | DSPIC33FJ64MC706A-E/PT |
|---|---|---|---|---|---|
| Package | 64-QFN with exposed pad (MR) | 64-QFN (MR) - same | 64-QFN (MR) - same | 64-QFN (MR) - same | 64-TQFP (PT) - different package |
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| Flash Program Memory | 64 KB | 128 KB | 32 KB | 64 KB | 64 KB |
| Core Performance | 40 MIPS / 40 MHz | 40 MIPS / 40 MHz | 40 MIPS / 40 MHz | 40 MIPS / 40 MHz | 40 MIPS / 40 MHz |
| Operating Temperature | -40C to +125C | -40C to +125C | -40C to +125C | -40C to +125C | -40C to +125C |
| CAN Controller | Yes (CAN 2.0B) | Yes (CAN 2.0B) | Yes (CAN 2.0B) | Yes (CAN 2.0B) | Yes (CAN 2.0B) |
| Container | Tube | Tube | Tube | Tape & Reel | Tube |
| Firmware Compatibility | Reference (dsPIC33FJ MC706A family) | Identical, more flash headroom | Identical, 50% flash limit | Identical (same die) | Identical firmware, different footprint |
Key Differentiators
- Extended -40C to +125C temperature grade at standard-family cost (vs DSPIC33FJ64MC506A-I/PT)
- Silicon errata corrections of the legacy part (vs DSPIC33FJ64MC706 (non-A))
- Exposed-pad QFN improves thermal and EMC performance (vs DSPIC33FJ64MC706A-E/PT)
- Trade-off: flash size fixed at 64 KB (vs DSPIC33FJ128MC706A-E/MR)
Design Notes
The 64-QFN exposed pad (pin EP) is not optional - it is the primary ground connection and thermal path for the die. Create a solder-mask-defined window in the PCB ground plane with an array of thermal vias (5x5 pattern, 0.3 mm drill) to tie the pad to internal ground layers, and use a stencil with approximately 50-70% pad coverage divided into multiple apertures to prevent solder voiding. All four VDD/VSS pairs plus AVDD/AVSS should each receive a 0.1 uF ceramic decoupling capacitor placed within 2 mm of the pins.
Power the core and I/O from a clean 3.3 V rail rated at least 100 mA for the DSC plus peripheral loads. Because the motor-control PWM edges switch multiple outputs simultaneously at 40 MHz-class rates, add 10 uF bulk capacitance near the QFN in addition to per-pin 0.1 uF ceramics. Keep the analog supply (AVDD, pin 55) isolated with an RC filter (e.g., 10 ohm + 1 uF) from the digital rail when ADC accuracy matters for motor current sampling. Estimated current consumption during full-speed PWM operation is well within a single low-noise LDO budget, but verify against the datasheet electrical characteristics for your clock configuration.
Three recurring pitfalls: (1) Selecting the -I temperature variant to save cost in designs that later get deployed in sealed enclosures - the E suffix (-40C to +125C) costs little more and prevents field failures. (2) Treating the non-A dsPIC33FJ64MC706 as a cheap substitute - the A revision exists specifically to fix legacy errata. (3) Leaving MCLR floating; always fit a 10 kOhm pull-up plus optional 0.1 uF to ground for reliable power-on reset and in-circuit programming with tools like PICkit or ICD. Also confirm the oscillator configuration fuses match your crystal before first programming to avoid lockout.
Route the PWM1L/H output pairs away from AN inputs and the CAN lines. When phase-current sensing uses shunt resistors, sample with the ADC synchronized to the PWM period center (trigger from the PWM module, not software delay) to avoid sampling during switch-node transients. Keep the C1RX/C1CAN traces short and matched to the transceiver, and terminate the CAN bus at both ends with 120 ohm per ISO 11898 topology conventions used in Microchip CAN reference designs.
Compliance Information
Compliance status was not stated in the verified web data; consult the Microchip product page or environmental datasheet for RoHS/REACH status of the -E/MR suffix.
