EP1M120F484C6ES - Mercury FPGA 120K Gates 484-FBGA | Intel / Altera
MPN: EP1M120F484C6ES ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $145 | $145.00 |
| 10 | $132.5 | $1,325.00 |
| 100 | $118 | $11,800.00 |
| 250 | $105 | $26,250.00 |
| 500 | $92.5 | $46,250.00 |
Drop-in alternatives for EP1M120F484C6ES — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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View Datasheet →EP1M120F484C6ES Maximum Ratings & Electrical Characteristics
| Family | Mercury (Altera / Intel) |
| System Gates | 120,000 |
| Logic Elements / Cells | 4,800 |
| Logic Array Blocks (LABs) | 480 |
| Embedded Memory (bits) | 49,152 |
| Maximum User I/O | 303 |
| Core Supply Voltage | 1.8 V |
| I/O Standards Supported | LVTTL, LVCMOS (1.5/1.8/2.5/3.3 V) |
| Configuration Technology | SRAM (volatile) |
| Package | 484-ball FC-FBGA |
| Mounting Type | Surface Mount (BGA) |
| Speed Grade | 6 (-6) |
| JTAG / Boundary Scan | Yes (IEEE 1149.1) |
| Part Status | Obsolete / last-time-buy (ES suffix = engineering sample) |
EP1M120F484C6ES Pin Configuration
| Pin A1 | I/O Bank 1 — User I/O (ball assignment varies by package revision) |
| Pin A2 | I/O Bank 1 — User I/O |
| Pin B1 | I/O Bank 1 — User I/O |
| Pin B2 | GND — Ground |
| Pin C1 | VCCIO1 — I/O bank 1 supply (1.5/1.8/2.5/3.3 V) |
| Pin C2 | I/O Bank 2 — User I/O |
| Pin D1 | I/O Bank 2 — User I/O |
| Pin D2 | VCCINT — Core supply (1.8 V) |
| Pin E1 | nCONFIG — Configuration control (active-low) |
| Pin E2 | nSTATUS — Configuration status (active-low) |
| Pin F1 | CONF_DONE — Configuration complete (open-drain) |
| Pin F2 | TCK — JTAG clock input |
| Pin G1 | TMS — JTAG mode select |
| Pin G2 | TDI — JTAG data in |
| Pin H1 | TDO — JTAG data out |
| Pin H2 | MSEL0 — Configuration mode select 0 |
| Pin J1 | MSEL1 — Configuration mode select 1 |
| Pin J2 | MSEL2 — Configuration mode select 2 |
| Pin K1 | CLK0 — Dedicated clock input 0 |
| Pin K2 | CLK1 — Dedicated clock input 1 |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EP1M120F484C6ES is suitable for 6 applications: Industrial Glue Logic and Bus Bridging, Telecom Line-Card Interface and Framing, Video and Image Processing Front-End, ASIC Prototyping and Emulation, Military and Aerospace Avionics (Legacy Programs), Legacy PCI / CPCI Bridge Card.
Industrial Glue Logic and Bus Bridging
The EP1M120F484C6ES is well matched to industrial glue-logic and protocol-bridging roles thanks to its 303 user I/O and 1.5 V-3.3 V LVCMOS/LVTTL I/O bank programmability. In a typical application the FPGA sits between a microcontroller and a parallel data acquisition bus, translating 8-bit parallel ADC output into a SPI or I2C stream for a host processor. The 4,800 logic elements are sufficient for state-machine-based protocol conversion at line rates up to ~50 MHz. Compared with a CPLD, the EP1M120F484C6ES provides more flip-flops and more flexible I/O placement, but it remains volatile - meaning the board must include an EPCS configuration PROM to load the bitstream at every power-up.
Recommended
Telecom Line-Card Interface and Framing
In telecom line cards the EP1M120F484C6ES serves as a programmable framer and protocol mapper between a network processor and the physical-layer transceiver. Its 49,152 bits of embedded RAM can buffer multiple T1/E1 or Ethernet frames, while the 303 I/O tolerate parallel connections to bus transceivers and clock-distribution chips. The 1.8 V core and 3.3 V-tolerant I/O make it compatible with classic telecom ASIC voltages. Engineers migrating to modern designs should evaluate the Cyclone IV EP4CE115F29I7N, which offers roughly 25x more logic capacity with a similar I/O count, but the EP1M120F484C6ES remains a cost-effective drop-in for legacy line cards already qualified for Mercury-family bitstreams.
Recommended
Video and Image Processing Front-End
The EP1M120F484C6ES fits legacy video front-end applications such as camera-link capture, BT.656 de-interlacing, and image pre-processing at resolutions up to 720p/60. The 4,800 logic elements provide the LUTs needed for pixel-pipeline stages (color-space conversion, gamma correction, edge detection), while the 49,152-bit block RAM supports line buffers of one or two video lines. The 484-ball FC-FBGA package exposes enough differential pairs for parallel RGB or LVDS input. Designers should note that the Mercury family lacks dedicated DSP blocks and hard memory controllers - all DSP and memory functions are synthesized in fabric - which caps the achievable pixel clock to roughly 65 MHz. For higher resolutions, use Cyclone IV or Lattice ECP5.
Recommended
ASIC Prototyping and Emulation
The EP1M120F484C6ES was historically used to prototype and emulate mid-complexity ASICs (100 K-130 K gates) before taping out. Its 4,800 logic elements combined with 49 Kbits of RAM can host most glue-logic and modest state-machine ASIC content, allowing firmware and software teams to develop against real silicon months ahead of the ASIC. Because the Mercury bitstream is SRAM-based, designers can iterate quickly by reloading from JTAG. Modern ASIC prototyping has moved to large FPGAs such as Cyclone V or Kintex-7, but the EP1M120F484C6ES remains useful for legacy programs with Mercury bitstreams already in production.
Recommended
Military and Aerospace Avionics (Legacy Programs)
The Mercury family has long service tails in military and aerospace programs that were qualified in the late 1990s and early 2000s. The EP1M120F484C6ES, in its industrial or military temperature grade variant, continues to support flight-control, mission-computer, and radar-signal-processing subsystems where re-design is prohibitively expensive. Its 1.8 V core, JTAG-based in-system programming, and BGA package all meet the ruggedization requirements typical of avionics LRUs. Because the family is obsolete, long-life programs must manage inventory carefully; XAIPART and authorized distributors of last resort (e.g., Heisener, IC-Components) carry broker stock for this purpose.
Recommended
Legacy PCI / CPCI Bridge Card
CompactPCI and VME bridge cards in legacy military, telecom, and industrial-control chassis used the Mercury FPGA to implement 32-bit PCI target/initiator interfaces, scatter-gather DMA controllers, and interrupt steering. The EP1M120F484C6ES provides the 303 I/O and 4,800 logic elements required for a full PCI 2.2 target controller plus DMA engine, while the 49 Kbit block RAM accommodates descriptor FIFOs. Engineers maintaining these systems should verify the configuration PROM contents and JTAG chain integrity, as the bitstream is volatile. For new PCI Express designs, migrate to Cyclone V GX or Kintex UltraScale.
Recommended
Recommended Products Summary
Engineering reference data for EP1M120F484C6ES — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP1M120F484C6 | EP1M120F484C5N | EP1M120F484C5 | EP1M120F484C5M | EP1M120F484-I6 |
|---|---|---|---|---|---|---|
| Package | 484-ball FC-FBGA | 484-ball FC-FBGA - same | 484-ball FC-FBGA - same | 484-ball FC-FBGA - same | 484-ball FC-FBGA - same | 484-ball FC-FBGA - same |
| Brand | Intel / Altera | Intel / Altera - same | Intel / Altera - same | Intel / Altera - same | Intel / Altera - same | Intel / Altera - same |
| Family | Mercury | Mercury - same | Mercury - same | Mercury - same | Mercury - same | Mercury - same |
| System Gates | 120 K | 120 K | 120 K | 120 K | 120 K | 120 K |
| Logic Elements | 4,800 | 4,800 | 4,800 | 4,800 | 4,800 | 4,800 |
| Embedded Memory (bits) | 49,152 | 49,152 | 49,152 | 49,152 | 49,152 | 49,152 |
| Maximum User I/O | 303 | 303 | 303 | 303 | 303 | 303 |
| Speed Grade | C6 (engineering sample) | C6 (production) | C5 | C5 | C5 military | C6 industrial |
| Temperature Grade | [DATA_NEEDED] | Commercial | Commercial | Commercial | Military | Industrial |
| Lifecycle Status | Obsolete (ES sample) | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- Same die as production Mercury parts with engineering-sample speed grade (vs EP1M120F484C6 (production version))
- Industry-standard 484-ball FC-FBGA package (vs EP1M120F484 (legacy ordering code))
- SRAM-based volatile configuration with standard JTAG (vs CPLDs (e.g., EPM7128SQC100))
Design Notes
Because the EP1M120F484C6ES is a 484-ball FC-FBGA device, PCB design must use microvia or via-in-pad stack-ups to fan out the 1.0 mm ball pitch. Maintain a continuous ground plane on layer 2 directly beneath the BGA and route signals on outer layers; place 0.1 uF decoupling capacitors on every VCCINT and VCCIO ball within 5 mm trace length. Add a 100 uF bulk tantalum or polymer cap near the FPGA's main supply pin to suppress switching transients during configuration.
Mercury FPGAs are SRAM-based and volatile, so a configuration PROM (EPCS4, EPCS16, or EPCS64) is mandatory. Power sequencing must bring up VCCINT (1.8 V) before VCCIO, and the nCONFIG pin must be held low until all supplies are stable. Use a power-on reset supervisor to drive nCONFIG reliably, and add a 10 kohm pull-up on nSTATUS and CONF_DONE as recommended by the Altera Mercury handbook.
All 303 user I/O of the EP1M120F484C6ES are organized into banks with independent supply voltages (1.5 V, 1.8 V, 2.5 V, or 3.3 V). Mixing voltages within a single bank will permanently damage the device; consult the Mercury Pin Information chapter for bank boundaries before PCB layout. For high-speed signals (above 50 MHz), use LVDS pairs and 100 ohm differential termination; for slower control signals, LVCMOS with 25-50 ohm series termination is usually sufficient.
Common pitfalls when designing with the EP1M120F484C6ES include: (1) forgetting that the bitstream is volatile and not providing a configuration PROM; (2) confusing the Mercury family with the older FLEX 10K or ACEX 1K families - the bitstream formats are incompatible; (3) ignoring the ES suffix and assuming production-grade reliability; (4) attempting to use 5 V signals directly on the I/O banks which will damage the device. Always cross-check the part marking against the Altera Mercury datasheet ordering guide before board bring-up.
Compliance Information
Compliance data not available in the verified web search results. The Mercury family predates many modern compliance certifications; specific lot markings should be verified with the distributor. Not AEC-Q100 qualified.
