EPM7160STC100-10 - MAX 7000S CPLD, 160 Macrocells, 100-pin TQFP | Intel
MPN: EPM7160STC100-10 β Last Time Buy| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $28.5 | $28.50 |
| 10 | $25.2 | $252.00 |
| 100 | $21.75 | $2,175.00 |
| 500 | $18.4 | $9,200.00 |
| 1,000 | $15.9 | $15,900.00 |
Drop-in alternatives for EPM7160STC100-10 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPM7160STC100-10N
β Drop-Inβ In Stock
$15.95 / Unit
View Datasheet βEPM7160STC100-7
β Drop-Inπ Reference alternative (not in catalog)
EPM7160STC100-15
β Drop-Inπ Reference alternative (not in catalog)
EPM7160STC100-6
β Drop-Inπ Reference alternative (not in catalog)
EPM7160STI100-10
β Drop-Inβ In Stock
$90.43 / Unit
View Datasheet βEPM7160STC100-10F
β Drop-Inβ In Stock
$9.95 / Unit
View Datasheet βEPM7160STC100-10 Maximum Ratings & Electrical Characteristics
| Family | MAX 7000S |
| Device Type | CPLD (Complex Programmable Logic Device) |
| Macro Cells | 160 |
| User I/Os | 84 |
| Usable Gates | 3,200 |
| Logic Elements | 160 macrocells / 10 Logic Array Blocks |
| Supply Voltage (VCC) | 5.0 V (4.75 V - 5.25 V) |
| Propagation Delay (tPD1) | 10 ns |
| Global Clock Setup Time | 6 ns |
| Internal Counter Frequency | 100 MHz |
| Technology | CMOS, EEPROM-based |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) |
| Package | 100-pin TQFP |
| Operating Temperature | 0 C to +70 C (commercial) |
| Mounting Type | Surface Mount |
| RoHS Status | Non-RoHS (legacy Altera part; -10N variant is RoHS) |
EPM7160STC100-10 Pin Configuration
| Pin 1 | I/O β User I/O pin (bank 1) |
| Pin 2 | I/O β User I/O pin (bank 1) |
| Pin 3 | I/O β User I/O pin (bank 1) |
| Pin 4 | I/O β User I/O pin (bank 1) |
| Pin 5 | I/O β User I/O pin (bank 1) |
| Pin 6 | I/O β User I/O pin (bank 1) |
| Pin 7 | I/O β User I/O pin (bank 1) |
| Pin 8 | I/O β User I/O pin (bank 1) |
| Pin 9 | I/O β User I/O pin (bank 1) |
| Pin 10 | I/O β User I/O pin (bank 1) |
| Pin 11 | I/O β User I/O pin (bank 1) |
| Pin 12 | TDI β JTAG Test Data In |
| Pin 13 | TMS β JTAG Test Mode Select |
| Pin 14 | TCK β JTAG Test Clock |
| Pin 15 | I/O β User I/O pin (bank 1) |
| Pin 16 | I/O β User I/O pin (bank 1) |
| Pin 17 | I/O β User I/O pin (bank 1) |
| Pin 18 | I/O β User I/O pin (bank 1) |
| Pin 19 | I/O β User I/O pin (bank 1) |
| Pin 20 | I/O β User I/O pin (bank 1) |
| Pin 21 | VCC β 5.0 V supply (bank 1) |
| Pin 22 | I/O β User I/O pin (bank 1) |
| Pin 23 | I/O β User I/O pin (bank 1) |
| Pin 24 | GCLK1 β Global clock input 1 |
| Pin 25 | OE1 β Global output enable 1 |
| Pin 26 | GCLRn β Global clear (active low) |
| Pin 27 | I/O β User I/O pin (bank 2) |
| Pin 28 | I/O β User I/O pin (bank 2) |
| Pin 29 | I/O β User I/O pin (bank 2) |
| Pin 30 | I/O β User I/O pin (bank 2) |
| Pin 31 | I/O β User I/O pin (bank 2) |
| Pin 32 | I/O β User I/O pin (bank 2) |
| Pin 33 | I/O β User I/O pin (bank 2) |
| Pin 34 | I/O β User I/O pin (bank 2) |
| Pin 35 | I/O β User I/O pin (bank 2) |
| Pin 36 | GND β Ground |
| Pin 37 | I/O β User I/O pin (bank 2) |
| Pin 38 | I/O β User I/O pin (bank 2) |
| Pin 39 | I/O β User I/O pin (bank 2) |
| Pin 40 | I/O β User I/O pin (bank 2) |
| Pin 41 | I/O β User I/O pin (bank 2) |
| Pin 42 | I/O β User I/O pin (bank 2) |
| Pin 43 | I/O β User I/O pin (bank 2) |
| Pin 44 | I/O β User I/O pin (bank 2) |
| Pin 45 | I/O β User I/O pin (bank 2) |
| Pin 46 | VCC β 5.0 V supply (bank 2) |
| Pin 47 | I/O β User I/O pin (bank 2) |
| Pin 48 | I/O β User I/O pin (bank 2) |
| Pin 49 | GCLK2 β Global clock input 2 |
| Pin 50 | OE2 β Global output enable 2 |
| Pin 51 | I/O β User I/O pin (bank 3) |
| Pin 52 | I/O β User I/O pin (bank 3) |
| Pin 53 | I/O β User I/O pin (bank 3) |
| Pin 54 | I/O β User I/O pin (bank 3) |
| Pin 55 | I/O β User I/O pin (bank 3) |
| Pin 56 | I/O β User I/O pin (bank 3) |
| Pin 57 | I/O β User I/O pin (bank 3) |
| Pin 58 | I/O β User I/O pin (bank 3) |
| Pin 59 | I/O β User I/O pin (bank 3) |
| Pin 60 | GND β Ground |
| Pin 61 | I/O β User I/O pin (bank 3) |
| Pin 62 | I/O β User I/O pin (bank 3) |
| Pin 63 | I/O β User I/O pin (bank 3) |
| Pin 64 | I/O β User I/O pin (bank 3) |
| Pin 65 | I/O β User I/O pin (bank 3) |
| Pin 66 | I/O β User I/O pin (bank 3) |
| Pin 67 | I/O β User I/O pin (bank 3) |
| Pin 68 | I/O β User I/O pin (bank 3) |
| Pin 69 | I/O β User I/O pin (bank 3) |
| Pin 70 | I/O β User I/O pin (bank 3) |
| Pin 71 | VCC β 5.0 V supply (bank 3) |
| Pin 72 | I/O β User I/O pin (bank 4) |
| Pin 73 | I/O β User I/O pin (bank 4) |
| Pin 74 | I/O β User I/O pin (bank 4) |
| Pin 75 | I/O β User I/O pin (bank 4) |
| Pin 76 | I/O β User I/O pin (bank 4) |
| Pin 77 | I/O β User I/O pin (bank 4) |
| Pin 78 | I/O β User I/O pin (bank 4) |
| Pin 79 | I/O β User I/O pin (bank 4) |
| Pin 80 | I/O β User I/O pin (bank 4) |
| Pin 81 | I/O β User I/O pin (bank 4) |
| Pin 82 | I/O β User I/O pin (bank 4) |
| Pin 83 | GND β Ground |
| Pin 84 | I/O β User I/O pin (bank 4) |
| Pin 85 | I/O β User I/O pin (bank 4) |
| Pin 86 | I/O β User I/O pin (bank 4) |
| Pin 87 | I/O β User I/O pin (bank 4) |
| Pin 88 | I/O β User I/O pin (bank 4) |
| Pin 89 | I/O β User I/O pin (bank 4) |
| Pin 90 | I/O β User I/O pin (bank 4) |
| Pin 91 | I/O β User I/O pin (bank 4) |
| Pin 92 | I/O β User I/O pin (bank 4) |
| Pin 93 | I/O β User I/O pin (bank 4) |
| Pin 94 | I/O β User I/O pin (bank 4) |
| Pin 95 | VCC β 5.0 V supply (bank 4) |
| Pin 96 | I/O β User I/O pin (bank 4) |
| Pin 97 | I/O β User I/O pin (bank 4) |
| Pin 98 | I/O β User I/O pin (bank 4) |
| Pin 99 | TDO β JTAG Test Data Out |
| Pin 100 | I/O β User I/O pin (bank 1) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM7160STC100-10 is suitable for 6 applications: Microprocessor Bus Glue Logic, Address Decoding & Chip-Select Generation, Industrial Control State Machines, Peripheral Interface Bridging (UART/SPI/I2C), Legacy TTL/CMOS Logic Integration, Test Equipment & JTAG Boundary-Scan Control.
Microprocessor Bus Glue Logic
The EPM7160STC100-10 is widely used as a glue-logic bridge between microprocessors and peripherals where deterministic 10 ns timing matters more than raw logic density. Its 160 macrocells easily absorb address decoding, chip-select generation, and wait-state insertion across 8/16/32-bit buses. The 5.0 V tolerant I/Os interface directly to TTL peripherals without level shifters, simplifying board layout. Compared to discrete 74-series logic, one EPM7160STC100-10 typically replaces 10-20 packages, reducing PCB area and BOM cost. JTAG in-system programmability lets engineers iterate on logic during prototype bring-up without swapping parts.
Recommended
Address Decoding & Chip-Select Generation
With 160 macrocells and 84 user I/Os, the EPM7160STC100-10 can decode large memory maps and generate chip-select signals for banks of memory-mapped peripherals simultaneously. Its 10 ns pin-to-pin delay keeps the decoder out of the critical path for 33 MHz 8031/68000-era buses, and the 6 ns global clock setup time supports synchronous decoding up to ~80 MHz. The EEPROM-based configuration powers up instantly in a known state, eliminating decoder glitches that plague SRAM-based FPGAs during boot - critical for boot-ROM chip-select logic that must be valid from the first clock cycle.
Recommended
Industrial Control State Machines
The deterministic timing and instant-on EEPROM configuration of the EPM7160STC100-10 make it ideal for industrial PLC state machines controlling stepper motors, solenoids, and conveyor sequencing. Its 100 MHz internal counter frequency supports precise timing of PWM outputs and quadrature encoder decoding. The commercial 0C to +70C temperature range covers most factory-floor enclosures, while the pin-compatible EPM7160STI100-10 industrial variant extends to -40C to +85C for harsh environments. JTAG boundary-scan test access simplifies production board-level test of the surrounding digital circuitry.
Recommended
Peripheral Interface Bridging (UART/SPI/I2C)
The EPM7160STC100-10 frequently bridges between incompatible peripheral interfaces - translating between SPI and parallel buses, multiplexing UARTs, or converting I2C to memory-mapped registers. Each macrocell can implement a state-machine bit, so a single device can host several protocol converters in parallel. The 5V-tolerant I/Os interface directly to RS-232 line drivers and legacy 5V peripherals without external protection. Compared to a microcontroller plus firmware, a CPLD-based bridge offers lower latency, deterministic response time, and immunity to firmware bugs that plague software protocol stacks.
Recommended
Legacy TTL/CMOS Logic Integration
The EPM7160STC100-10 is a drop-in consolidation device for legacy boards built from discrete 74LS, 74HC, and 74F logic gates, latches, and counters. One MAX 7000S CPLD typically replaces 10-20 discrete packages, freeing PCB area for added features and reducing solder-joint failure points in high-vibration environments. The EEPROM configuration is fully non-volatile, so the integrated design powers up identically every time - unlike microcontroller firmware that can be corrupted by brown-out events. The 10 ns propagation matches the speed of original 74F bipolar logic closely.
Recommended
Test Equipment & JTAG Boundary-Scan Control
Beyond its own JTAG ISP interface, the EPM7160STC100-10 is widely used as a JTAG controller in test fixtures and boundary-scan test access port (TAP) aggregators for boards with mixed CPLD/FPGA/MCU devices. Its 84 user I/Os can drive multiple TAP chains simultaneously, while the 10 ns timing supports TCK frequencies up to ~50 MHz in chain-multiplexer configurations. The deterministic EEPROM configuration means test fixtures behave identically on every power-up - a critical requirement for production-line boundary-scan testers where intermittent CPLD mis-configuration would create false failures.
Recommended
Recommended Products Summary
Engineering reference data for EPM7160STC100-10 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM7160STC100-10N | EPM7160STC100-7 | EPM7160STC100-15 | EPM7160STC100-6 | EPM7160STI100-10 | EPM7160STC100-10F |
|---|---|---|---|---|---|---|---|
| Package | TQFP-100 | TQFP-100 - same | TQFP-100 - same | TQFP-100 - same | TQFP-100 - same | TQFP-100 - same | TQFP-100 - same |
| Brand | Intel (formerly Altera) | Intel | Intel | Intel | Intel | Intel | Intel |
| Macro Cells | 160 | 160 | 160 | 160 | 160 | 160 | 160 |
| User I/Os | 84 | 84 | 84 | 84 | 84 | 84 | 84 |
| Propagation Delay (tPD1) | 10 ns | 10 ns | 7 ns | 15 ns | 6 ns | 10 ns | 10 ns |
| Supply Voltage | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V |
| Operating Temperature | 0C to +70C (commercial) | 0C to +70C | 0C to +70C | 0C to +70C | 0C to +70C | -40C to +85C (industrial) | 0C to +70C |
| RoHS Compliance | Non-RoHS (legacy) | RoHS compliant | Non-RoHS (legacy) | Non-RoHS (legacy) | Non-RoHS (legacy) | Non-RoHS (legacy) | Lead-free finish |
| Family | MAX 7000S | MAX 7000S | MAX 7000S | MAX 7000S | MAX 7000S | MAX 7000S | MAX 7000S |
Key Differentiators
- Largest logic capacity in MAX 7000S TQFP-100 family (vs EPM7128STC100-10)
- Balanced speed grade for mid-frequency designs (vs EPM7160STC100-7)
- Direct RoHS migration path available (vs EPM7160STC100-10N)
Design Notes
The EPM7160STC100-10 requires a stable 5.0 V supply with 4.75 V to 5.25 V tolerance per the MAX 7000S datasheet. Place 0.1 uF decoupling capacitors within 5 mm of every VCC pin (4 pins total: pins 21, 46, 71, 95) and add a 10 uF bulk capacitor near the package. During in-system programming via JTAG, VCC must rise monotonically - any brownout during configuration can leave the EEPROM in an indeterminate state requiring re-programming.
The 10 ns tPD1 propagation delay of the EPM7160STC100-10 requires careful PCB layout for clock and asynchronous signal routing. Keep global clock traces (GCLK1 pin 24, GCLK2 pin 49) shorter than 25 mm with 50 ohm characteristic impedance. Use series termination resistors (33-68 ohm) on clock outputs driving multiple loads. The 6 ns global clock setup time supports synchronous designs up to ~80 MHz internal frequency when clock skew is held under 1 ns across the chip.
Do not confuse the EPM7160STC100-10 (commercial temp, 10 ns) with the EPM7160STI100-10 (industrial -40C to +85C temp, 10 ns) - they are NOT interchangeable in production bins. The pin-compatible EPM7160SQC160-10 uses a 160-pin PQFP package, NOT 100-pin TQFP - attempting to substitute it on a TQFP-100 PCB will fail. When migrating legacy designs, always verify exact package code (STC=TQFP-100, SQC=PQFP-160, SLC=PLCC-84, SLI=PLCC-84 industrial) before ordering.
The TQFP-100 package has a 0.5 mm pitch and 1.6 mm height profile. Allow at least 0.2 mm solder mask expansion and use NSMD (non-solder mask defined) pads for reliable paste release during reflow. For hand-prototyping, use a TQFP-100 breakout board or adapter; the 0.5 mm pitch is below the practical limit for hand-soldering with a standard iron. A hot-air rework station with a TQFP nozzle is recommended for prototype rework.
Compliance Information
Original EPM7160STC100-10 is non-RoHS leaded Altera part. The -10N suffix variant is RoHS compliant with lead-free finish. Pin-compatible RoHS variant EPM7160STC100-10N recommended for new EU-market designs.
