EPM7160STI100-10 - MAX 7000S CPLD, 160 Macrocells, 100MHz | Altera
MPN: EPM7160STI100-10 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $110 | $110.00 |
| 10 | $100 | $1,000.00 |
| 100 | $96 | $9,600.00 |
| 500 | $93 | $46,500.00 |
| 2,800 | $90.43 | $253,204.00 |
Drop-in alternatives for EPM7160STI100-10 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EPM7160STI100-10N
✅ Drop-In✓ In Stock
$7.8 / Unit
View Datasheet →EPM7160STC100-10N
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$15.95 / Unit
View Datasheet →EPM7160STC100-10
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$15.9 / Unit
View Datasheet →EPM7160SQC160-10
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$12.2 / Unit
View Datasheet →EPM7160SQC160-10N
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$8.1 / Unit
View Datasheet →EPM7160EQC100-20
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$17.1 / Unit
View Datasheet →EPM7160EQC160-12
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View Datasheet →EPM7160STI100-10 Maximum Ratings & Electrical Characteristics
| Family | MAX 7000S |
| Macrocells | 160 |
| Usable Gates | 3,200 |
| User I/Os | 84 |
| Logic Elements / Blocks | 16 Logic Array Blocks (LABs) |
| Propagation Delay (tPD) | 10 ns |
| Maximum Operating Frequency | 100 MHz |
| Internal Supply Voltage | 4.75 V to 5.25 V |
| I/O Supply Voltage | 5.0 V |
| Programmable Type | In-System Programmable (EEPROM) |
| Operating Temperature | -40 C to +85 C (Industrial) |
| Package | TQFP-100 (100-pin Thin Quad Flat Pack) |
| Mounting Type | Surface Mount |
| JTAG / Boundary Scan | IEEE Std. 1149.1 compliant |
| PCI Compliance | PCI Local Bus Specification Rev. 2.2 (for -10 speed grade) |
EPM7160STI100-10 Pin Configuration
| Pin 1 | GND — Ground reference |
| Pin 2 | I/O — User I/O pin (macrocell 1) |
| Pin 3 | I/O — User I/O pin |
| Pin 4 | I/O — User I/O pin |
| Pin 5 | I/O — User I/O pin |
| Pin 6 | I/O — User I/O pin |
| Pin 7 | I/O — User I/O pin |
| Pin 8 | I/O — User I/O pin |
| Pin 9 | VCCINT — Internal core supply (5V) |
| Pin 10 | I/O — User I/O pin |
| Pin 11 | GND — Ground |
| Pin 12 | I/O — User I/O pin |
| Pin 13 | I/O — User I/O pin |
| Pin 14 | I/O — User I/O pin |
| Pin 15 | I/O — User I/O pin |
| Pin 16 | TDI — JTAG Test Data In |
| Pin 17 | TMS — JTAG Test Mode Select |
| Pin 18 | TCK — JTAG Test Clock |
| Pin 19 | I/O — User I/O pin |
| Pin 20 | GND — Ground |
| Pin 21 | I/O — User I/O pin |
| Pin 22 | I/O — User I/O pin |
| Pin 23 | I/O — User I/O pin |
| Pin 24 | I/O — User I/O pin |
| Pin 25 | VCCIO — I/O supply (5V) |
| Pin 26 | I/O — User I/O pin |
| Pin 27 | GND — Ground |
| Pin 28 | I/O — User I/O pin |
| Pin 29 | I/O — User I/O pin |
| Pin 30 | INPUT/GCLK — Dedicated input or global clock |
| Pin 31 | I/O — User I/O pin |
| Pin 32 | I/O — User I/O pin |
| Pin 33 | I/O — User I/O pin |
| Pin 34 | I/O — User I/O pin |
| Pin 35 | I/O — User I/O pin |
| Pin 36 | I/O — User I/O pin |
| Pin 37 | VCCINT — Internal core supply |
| Pin 38 | GND — Ground |
| Pin 39 | I/O — User I/O pin |
| Pin 40 | I/O — User I/O pin |
| Pin 41 | I/O — User I/O pin |
| Pin 42 | I/O — User I/O pin |
| Pin 43 | I/O — User I/O pin |
| Pin 44 | OE1 — Output Enable 1 (global) |
| Pin 45 | I/O — User I/O pin |
| Pin 46 | GND — Ground |
| Pin 47 | I/O — User I/O pin |
| Pin 48 | I/O — User I/O pin |
| Pin 49 | I/O — User I/O pin |
| Pin 50 | I/O — User I/O pin |
| Pin 51 | VCCIO — I/O supply |
| Pin 52 | I/O — User I/O pin |
| Pin 53 | GND — Ground |
| Pin 54 | I/O — User I/O pin |
| Pin 55 | I/O — User I/O pin |
| Pin 56 | I/O — User I/O pin |
| Pin 57 | I/O — User I/O pin |
| Pin 58 | OE2/GCLK2 — Output Enable 2 or global clock 2 |
| Pin 59 | I/O — User I/O pin |
| Pin 60 | I/O — User I/O pin |
| Pin 61 | I/O — User I/O pin |
| Pin 62 | I/O — User I/O pin |
| Pin 63 | VCCINT — Internal core supply |
| Pin 64 | GND — Ground |
| Pin 65 | I/O — User I/O pin |
| Pin 66 | I/O — User I/O pin |
| Pin 67 | I/O — User I/O pin |
| Pin 68 | I/O — User I/O pin |
| Pin 69 | I/O — User I/O pin |
| Pin 70 | I/O — User I/O pin |
| Pin 71 | I/O — User I/O pin |
| Pin 72 | CLR — Global clear (active low) |
| Pin 73 | I/O — User I/O pin |
| Pin 74 | GND — Ground |
| Pin 75 | I/O — User I/O pin |
| Pin 76 | I/O — User I/O pin |
| Pin 77 | I/O — User I/O pin |
| Pin 78 | I/O — User I/O pin |
| Pin 79 | VCCIO — I/O supply |
| Pin 80 | I/O — User I/O pin |
| Pin 81 | GND — Ground |
| Pin 82 | I/O — User I/O pin |
| Pin 83 | I/O — User I/O pin |
| Pin 84 | I/O — User I/O pin |
| Pin 85 | I/O — User I/O pin |
| Pin 86 | I/O — User I/O pin |
| Pin 87 | I/O — User I/O pin |
| Pin 88 | I/O — User I/O pin |
| Pin 89 | VCCINT — Internal core supply |
| Pin 90 | GND — Ground |
| Pin 91 | I/O — User I/O pin |
| Pin 92 | I/O — User I/O pin |
| Pin 93 | I/O — User I/O pin |
| Pin 94 | I/O — User I/O pin |
| Pin 95 | I/O — User I/O pin |
| Pin 96 | INPUT — Dedicated input pin |
| Pin 97 | TDO — JTAG Test Data Out |
| Pin 98 | GND — Ground |
| Pin 99 | I/O — User I/O pin |
| Pin 100 | I/O — User I/O pin |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM7160STI100-10 is suitable for 6 applications: PCI Bus Interface Logic, Microprocessor Peripheral Glue Logic, Industrial Automation State Machines, Bus Arbitration and Address Decoding, Legacy 5V TTL/CMOS Logic Integration, JTAG-ISP Reprogrammable Logic Cores.
PCI Bus Interface Logic
The EPM7160STI100-10's 10ns tPD speed grade is explicitly PCI Local Bus Specification Revision 2.2 compliant, making it ideal for implementing PCI target and bridge interfaces in 33 MHz PCI systems. Its 84 user I/Os accommodate the 32-bit multiplexed AD/C/BE bus plus PAR, FRAME#, IRDY#, TRDY#, STOP#, DEVSEL#, IDSEL, and PAR64 signals with room to spare for sideband controls. The 5.0V I/O tolerance directly matches classic PCI signaling levels without level shifters, and the 160 macrocells provide ample capacity for address decoding, command handling, and state-machine logic.
Recommended
Microprocessor Peripheral Glue Logic
The EPM7160STI100-10 excels as a single-chip replacement for dozens of 74-series TTL/CMOS glue-logic packages in 5V microprocessor systems. The 160 macrocells and 84 user I/Os can implement address decoding, chip-select generation, wait-state insertion, bus arbitration, and interrupt prioritization in one device, dramatically simplifying PCB layout and reducing BOM cost. Its 10ns propagation delay ensures deterministic timing for fast 8051, x86, or 68k bus cycles without metastability, and EEPROM-based in-system programmability allows last-minute logic changes via JTAG without re-spinning the PCB.
Recommended
Industrial Automation State Machines
The EPM7160STI100-10's industrial -40C to +85C temperature range (denoted by the I suffix) makes it well-suited for factory-floor controllers, PLC I/O expansion modules, and motor-control glue logic. Its deterministic 10ns timing ensures reliable state-machine transitions in safety-critical sequencing logic, while the 160 macrocells allow multi-axis stepper/servo control state machines to coexist with fieldbus interface logic (e.g., Modbus, Profibus, CAN). The 5V I/O interfaces directly with industrial 24V-sensed opto-isolated inputs via pull-ups, eliminating level translators.
Recommended
Bus Arbitration and Address Decoding
For multi-master bus architectures such as VME, ISA, Multibus, or custom backplanes, the EPM7160STI100-10 provides dedicated bus arbitration logic with deterministic timing. Its 84 user I/Os comfortably handle 32-bit address plus 32-bit data plus arbitration control signals (BUSREQ, BUSGRANT, BUSACK) for multiple masters. The EEPROM non-volatile storage means configuration is retained across power cycles with no boot delay, critical for instant-on industrial systems. 160 macrocells are sufficient to implement priority encoders, address-decoder PLAs, and DMA handshake controllers in a single chip.
Recommended
Legacy 5V TTL/CMOS Logic Integration
The EPM7160STI100-10's 5.0V core and 5.0V-tolerant I/Os make it a direct replacement for legacy 74LS, 74HC, 74F, 74AS, and 4000-series CMOS logic boards that cannot easily migrate to 3.3V. With 160 macrocells equating to roughly 400-500 discrete gates, one CPLD can replace an entire logic cage of TTL packages while reducing power consumption and board area. Its deterministic 10ns delay eliminates the timing skew problems of discrete TTL cascades, and JTAG-ISP allows board-level logic changes for prototypes without reworking components.
Recommended
JTAG-ISP Reprogrammable Logic Cores
The EPM7160STI100-10's built-in IEEE 1149.1 JTAG interface and in-system programmability (ISP) enable field-upgradable logic without removing the device from the board. With 160 macrocells, designers can implement modular logic cores that are reconfigured via JTAG for firmware updates, design revisions, or feature enablement in production. This is particularly valuable for telecom infrastructure, military systems, and aerospace applications where board-level rework is impractical. The EEPROM cells support thousands of program/erase cycles, supporting in-field updates over the product lifetime.
Recommended
Recommended Products Summary
Engineering reference data for EPM7160STI100-10 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM7160STI100-10N | EPM7160STC100-10N | EPM7160STC100-10 | EPM7160SQC160-10 | EPM7160SQC160-10N | EPM7160EQC100-20 | EPM7160EQC160-12 |
|---|---|---|---|---|---|---|---|---|
| Package | TQFP-100 | TQFP-100 - same | TQFP-100 - same | TQFP-100 - same | TQFP-100 - same | TQFP-100 - same | TQFP-100 - same | TQFP-100 - same |
| Brand | Altera (Intel) | Altera (Intel) - same | Altera (Intel) - same | Altera (Intel) - same | Altera (Intel) - same | Altera (Intel) - same | Altera (Intel) - same | Altera (Intel) - same |
| Macrocells | 160 | 160 | 160 | 160 | 160 | 160 | 160 | 160 |
| Propagation Delay (tPD) | 10 ns | 10 ns | 10 ns | 10 ns | 10 ns | 10 ns | 20 ns | 12 ns |
| Maximum Frequency | 100 MHz | 100 MHz | 100 MHz | 100 MHz | 100 MHz | 100 MHz | [DATA_NEEDED] | [DATA_NEEDED] |
| Operating Temperature | -40 C to +85 C (Industrial) | -40 C to +85 C (Industrial) | 0 C to +70 C (Commercial) | 0 C to +70 C (Commercial) | [DATA_NEEDED] | [DATA_NEEDED] | 0 C to +70 C (Commercial) | 0 C to +70 C (Commercial) |
| Lead-Free / RoHS | Leaded (non-N suffix) | Lead-free (N suffix) | Lead-free (N suffix) | Leaded | Leaded | Lead-free | [DATA_NEEDED] | [DATA_NEEDED] |
| User I/Os | 84 | 84 | 84 | 84 | 84 | 84 | 84 | 84 |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- Industrial temperature grade for harsh environments (vs EPM7160STC100-10)
- Leaded solder finish (legacy compatibility) (vs EPM7160STI100-10N)
- Same-density die in 10ns speed grade (vs EPM7160EQC100-20)
Design Notes
The EPM7160STI100-10 requires a stable 5.0 V supply on both VCCINT (core) and VCCIO (I/O) rails. Decoupling must include a 0.1 uF ceramic capacitor on each VCCINT/VCCIO pin placed within 5 mm of the pin, plus a 10 uF tantalum or aluminum polymer bulk capacitor at the regulator output. Power sequencing is not required between VCCINT and VCCIO, but the supply must rise monotonically from 0 V to 5 V to ensure proper EEPROM initialization. Estimated: total core current is approximately 200-400 mA at 100 MHz with all I/O toggling; verify with actual design activity factor.
The TQFP-100 package has 0.5 mm lead pitch requiring careful PCB layout. Use 0.2 mm trace width with 0.2 mm spacing between pads, and place a continuous ground plane on layer 2 to provide controlled impedance for high-speed signals. Route JTAG signals (TCK, TMS, TDI, TDO) with series 33 ohm termination resistors at the driver to suppress ringing; TCK in particular must be kept short to avoid clock distortion. Place decoupling capacitors on the same layer as the CPLD, never buried, to minimize loop inductance.
Do not attempt to use the EPM7160STI100-10 in 3.3V-only systems; both VCCINT and VCCIO require 5V supply per the MAX 7000 datasheet. Exceeding the absolute maximum VCC of 7V will permanently damage the device. Do not leave unused I/O pins floating; configure them as outputs driving low or as inputs with internal pull-ups enabled in the Quartus pin assignment. When programming via JTAG, ensure the JTAG chain does not include devices that interfere with the instruction register; chain ordering matters for ISP.
The 100 MHz internal frequency translates to roughly 10 ns edge rates on I/O pins, which generates significant harmonic content. For clock outputs or high-speed bus interfaces, consider series damping resistors (22-33 ohm) at the CPLD output to control overshoot and ringing on the PCB trace. For long traces (>50 mm), use controlled-impedance routing (50 ohm microstrip) and ensure the far-end termination matches. The 5V CMOS outputs have typical drive strength of 4-8 mA per pin - sufficient for short traces but marginal for long backplane connections; use buffers for long traces.
Compliance Information
RoHS, REACH, lead-free, halogen-free, and conflict-minerals compliance information was not explicitly stated in the provided verified web data. The 'I' suffix denotes industrial temperature grade, and the 'N' suffix variant (EPM7160STI100-10N) is lead-free / RoHS-compliant. The base EPM7160STI100-10 (without N suffix) uses leaded solder finish. AEC-Q100 is not applicable because this is a programmable logic device, not an automotive-grade IC.
