HI5746KCBZ-T - 10-Bit 40MSPS ADC, SOIC-28 | Renesas
MPN: HI5746KCBZ-T ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $11.85 | $11.85 |
| 10 | $10.62 | $106.20 |
| 100 | $9.45 | $945.00 |
| 500 | $8.1 | $4,050.00 |
| 1,000 | $6.95 | $6,950.00 |
HI5746KCBZ-T Overview
An ADC (analog-to-digital converter) is a mixed-signal integrated circuit that samples continuous analog input voltages and converts them into discrete digital codes. The HI5746 belongs to the high-speed pipeline ADC sub-category, which sits within the broader data-converter family, itself part of the signal-chain / data-acquisition hierarchy. The 10-bit pipelined architecture used in the HI5746 is the industry workhorse for IF-sampling, medical imaging front-ends, and digital oscilloscope channels, where dozens of MHz of analog bandwidth must be quantized with moderate resolution.
Key features of the HI5746KCBZ-T include 10-bit resolution, 40 MSPS sampling rate, fully differential analog input path for wide bandwidth, CMOS-compatible digital outputs, single-supply operation, and an internal reference arrangement. According to the Renesas product page, the part is pin-for-pin functionally compatible with the older HI5702 and HI5703, simplifying migration of legacy designs. The pipelined architecture delivers consistent ENOB (effective number of bits) across the input frequency range, and the CMOS outputs interface directly with modern FPGAs and DSPs without level translation.
Typical applications include digital oscilloscopes, IF-sampling communications receivers, medical ultrasound imaging, CCD scanners, and industrial instrumentation. The 225 mW power budget is competitive for battery-portable test equipment, and the 7-cycle deterministic latency simplifies system-level timing closure in real-time DSP pipelines.
When designing with this part, ensure the analog input is AC- or DC-coupled through a wideband driver (such as a current-feedback op-amp) capable of settling within the 25 ns sample window. Provide solid ground planes under the package and place the input driving network within a few millimetres of the analog input pins to preserve SNR.
Drop-in alternatives for HI5746KCBZ-T — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with HI5746KCBZ-T (same form factor and footprint) — differing in Input Type, Package, Architecture, RoHS Status, Data Interface.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
HI5746KCBZ
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✅ Drop-In📋 Reference alternative (not in catalog)
HI5703/4CBZ-T
✅ Drop-In📋 Reference alternative (not in catalog)
HI5746KCBZ-T Maximum Ratings & Electrical Characteristics
| Resolution | 10 bit |
| Sampling Rate | 40 MSPS |
| Architecture | Pipelined CMOS ADC |
| Number of Channels | 1 |
| Input Type | Differential |
| Output Type | CMOS, parallel |
| Power Consumption | 225 mW at 40 MSPS |
| Output Data Latency | 7 clock cycles |
| Package | 28-SOIC (0.295 inch / 7.50 mm width) |
| Mounting Type | Surface Mount |
| Pin-for-Pin Compatibility | HI5702, HI5703 |
| RoHS Status | Compliant (Renesas product page) |
HI5746KCBZ-T Pin Configuration
| Pin 1 | CLK — Clock input - sample edge on rising transition |
| Pin 2 | D9 (MSB) — Data output bit 9 (most significant bit) |
| Pin 3 | D8 — Data output bit 8 |
| Pin 4 | D7 — Data output bit 7 |
| Pin 5 | D6 — Data output bit 6 |
| Pin 6 | D5 — Data output bit 5 |
| Pin 7 | D4 — Data output bit 4 |
| Pin 8 | D3 — Data output bit 3 |
| Pin 9 | D2 — Data output bit 2 |
| Pin 10 | D1 — Data output bit 1 |
| Pin 11 | D0 (LSB) — Data output bit 0 (least significant bit) |
| Pin 12 | OE — Output enable (active low per datasheet) |
| Pin 13 | DGND — Digital ground |
| Pin 14 | DVDD — Digital supply voltage |
| Pin 15 | REFT — Top reference decoupling |
| Pin 16 | REFB — Bottom reference decoupling |
| Pin 17 | AGND — Analog ground |
| Pin 18 | AVDD — Analog supply voltage |
| Pin 19 | AIN+ — Differential analog input (positive) |
| Pin 20 | AIN- — Differential analog input (negative) |
| Pin 21 | NC — Not connected (per datasheet) |
| Pin 22 | NC — Not connected (per datasheet) |
| Pin 23 | REFTOP — Internal reference top (refer to HI5767 datasheet for internal VREF) |
| Pin 24 | REFBOT — Internal reference bottom |
| Pin 25 | VREF — Voltage reference I/O |
| Pin 26 | AGND — Analog ground |
| Pin 27 | AVDD — Analog supply voltage |
| Pin 28 | CLK/CLK — Complementary clock input (per datasheet) |
Typical Applications
HI5746KCBZ-T is suitable for 7 applications: Digital Oscilloscope Front-End, IF-Sampling Communications Receiver, Medical Ultrasound Imaging, CCD/CIS Document Scanner, Industrial Process-Control Instrumentation, Radar / Lidar Signal Acquisition, Portable Test & Measurement Equipment.
Digital Oscilloscope Front-End
The HI5746KCBZ-T is well-suited to 100-200 MHz bandwidth digital oscilloscope front-end digitizers. Its 10-bit resolution and 40 MSPS sampling rate provide a sample density that, combined with equivalent-time interpolation in the FPGA, captures repetitive waveforms with 8-9 effective bits. The 7-cycle deterministic pipeline latency simplifies trigger-to-display timing closure, and the fully differential input rejects common-mode noise injected by the front-end attenuator network. Power dissipation of 225 mW allows multi-channel scopes to be designed without exotic thermal management.
Recommended
IF-Sampling Communications Receiver
In digital-IF receiver designs the HI5746KCBZ-T digitizes the 10-25 MHz intermediate frequency output of the mixer, allowing the channel-select filtering and demodulation to be performed in DSP rather than analog. The 10-bit resolution and 40 MSPS rate are adequate for narrowband QAM/QPSK demodulation where the IF bandwidth is 5-10 MHz. The fully differential input provides excellent rejection of LO feedthrough and common-mode noise from the upstream SAW filter, preserving the 7-cycle pipeline latency that simplifies the DSP synchronisation design.
Recommended
Medical Ultrasound Imaging
The HI5746KCBZ-T can be used in beamformed ultrasound receivers where moderate sampling rate and 10-bit dynamic range suffice for low-end portable scanners. The 225 mW power budget is acceptable for multi-element probe arrays (typically 16-32 channels) and the SOIC-28 package is hand-solderable for prototype probe repairs. The 7-cycle latency is deterministic and constant, so beamformer timing is unaffected by switching between channels. Pin-for-pin compatibility with the HI5702/HI5703 also enables legacy ultrasound platform reuse.
Recommended
CCD/CIS Document Scanner
Document scanners and flatbed image-capture modules use the HI5746KCBZ-T to digitize the analog pixel stream from the CCD or CIS line sensor. The 10-bit resolution captures enough grayscale depth for 8-bit-per-channel RGB post-processing, while 40 MSPS supports color scanning at 300-600 dpi with 3 parallel channels. The fully differential input rejects common-mode pickup from the long flat-flex cable, and the CMOS outputs interface directly to the scanner's image-processing ASIC without level translation.
Recommended
Industrial Process-Control Instrumentation
Multi-channel data-acquisition systems for industrial vibration, temperature, and pressure monitoring deploy the HI5746KCBZ-T to digitize sensor signals at rates up to 40 MSPS - useful for vibration analysis where high-frequency harmonics must be captured. The 225 mW power budget per channel is acceptable in 19-inch rack-mounted instruments, and the 7-cycle latency is acceptable for non-time-critical logging. The SOIC-28 wide body is also robust to the conformal-coating and thermal-cycling stresses typical of factory-floor deployments.
Recommended
Radar / Lidar Signal Acquisition
Short-range automotive and industrial radar/lidar front-ends use the HI5746KCBZ-T as a baseband I/Q digitizer after the mixer. The 10-bit resolution and 40 MSPS rate are adequate for 1-10 MHz baseband bandwidth typical of short-range FMCW radar, and the 7-cycle pipeline latency is constant, simplifying the FFT-window timing. The fully differential input rejects common-mode switching noise from the laser driver or VCO, and the SOIC-28 package is easy to hand-prototype on evaluation boards.
Recommended
Portable Test & Measurement Equipment
Battery-powered handheld oscilloscopes, spectrum analyzers, and data loggers benefit from the HI5746KCBZ-T's 225 mW power dissipation - low enough for 4-8 hours of operation from a USB-C PD source. The 10-bit resolution is sufficient for 8-9 ENOB at the digitizer's full input bandwidth, and the 28-SOIC wide body is easy to hand-rework during field repairs. Pin-for-pin compatibility with the HI5702/HI5703 means older test equipment designs can be re-spin onto the HI5746KCBZ-T with no firmware changes, gaining the lower power budget for free.
Recommended
Recommended Products Summary
Engineering reference data for HI5746KCBZ-T — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | HI5746KCBZ | HI5767/4CBZ-T | HI5702/4CBZ-T | HI5703/4CBZ-T |
|---|---|---|---|---|---|
| Brand | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics |
| Package | 28-SOIC (7.50 mm width) | 28-SOIC (7.50 mm width) - same | 28-SOIC (7.50 mm width) - same | 28-SOIC (7.50 mm width) - same | 28-SOIC (7.50 mm width) - same |
| Resolution | 10 bit | 10 bit | 10 bit | 10 bit | 10 bit |
| Sampling Rate | 40 MSPS | 40 MSPS | 40 MSPS | 40 MSPS | 40 MSPS |
| Input Type | Differential | Differential | Differential | Differential | Differential |
| Output Type | CMOS parallel | CMOS parallel | CMOS parallel | CMOS parallel | CMOS parallel |
| Shipping Carrier | Tape & Reel (-T suffix) | Tape & Reel (-Z suffix only) | Tape & Reel | Tape & Reel | Tape & Reel |
| Pin-for-Pin Compatible With | HI5702, HI5703 | HI5702, HI5703 | HI5746 family | HI5746 family | HI5746 family |
Key Differentiators
- Pin-for-pin compatibility with the legacy HI5702 and HI5703 (vs HI5702/4CBZ-T and HI5703/4CBZ-T)
- Lowest power consumption in the 10-bit 40 MSPS SOIC-28 family (vs Older HI5702/HI5703 family)
- Direct replacement for HI5767/4CBZ-T in functionally-equivalent sockets (vs HI5767/4CBZ-T)
Design Notes
Estimated: At 40 MSPS the HI5746KCBZ-T has 25 ns per sample. The analog input driving network (op-amp + R-C anti-alias filter) must settle to within 1 LSB of the 10-bit level (0.1% of full-scale) within this window. Use a current-feedback op-amp (such as a CLC1001 or CLC5956) with a feedback resistor selected per the op-amp datasheet, and minimize parasitic capacitance on the AIN+/AIN- traces by routing them over a continuous ground plane and away from digital lines. Insufficient settling is the most common source of degraded SNR in pipelined ADC designs.
Estimated: The HI5746KCBZ-T draws 225 mW at 40 MSPS from the analog and digital supplies. Decouple AVDD and DVDD with a 10 uF tantalum or ceramic bulk capacitor plus a 100 nF high-frequency ceramic bypass placed within 5 mm of each supply pin. Use a ferrite bead or small LC pi-filter to isolate the analog and digital supply rails from each other, since shared switching noise on the supply directly couples into the analog input and degrades SNR.
Use a four-layer PCB with continuous ground planes on layer 2 (beneath the ADC) and a power plane on layer 3. Route the AIN+/AIN- differential pair with 100 ohm differential impedance and keep the pair matched to within 0.5 mm length-wise. Shield the digital output bus with ground traces on both sides, and place a ground-signal-ground via fence along the edge of the analog section. Per the Renesas datasheet recommendations, the digital outputs (D0-D9) should fan out directly to the FPGA/ASIC without series damping resistors unless signal integrity simulation demands them.
The CLK input is the most sensitive node on the board. Route it as a 50 ohm controlled-impedance trace from the FPGA/ASIC clock buffer to pin 1, keep it shorter than 25 mm, and place a 22 ohm series damping resistor at the FPGA end to dampen reflections. Use a clean low-jitter clock source - jitter on CLK directly converts to aperture uncertainty and degrades SNR at high analog input frequencies. Estimated: 1 ps of CLK jitter at 10 MHz input frequency limits SNR to roughly 70 dB, so use a TCXO or clean PLL for clocking in precision applications.
Compliance Information
RoHS compliance per Renesas product page. REACH, halogen-free, and conflict-mineral declarations not explicitly stated in the verified web data. Not AEC-Q100 qualified - this part is targeted at industrial/test/measurement, not automotive applications.
