LPC1317FBD64,551 - 72MHz Cortex-M3 MCU 64KB Flash | NXP
料号： LPC1317FBD64,551 ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $9.11 | $9.11 |
| 10 | $8.45 | $84.50 |
| 100 | $7.1 | $710.00 |
| 500 | $6.05 | $3,025.00 |
| 1,000 | $5.2 | $5,200.00 |
LPC1317FBD64,551 概述
A microcontroller (MCU) is a single-chip computer that integrates a CPU core, program and data memory, and a wide range of peripherals such as timers, communication interfaces, ADC/DAC blocks, and GPIO. MCUs sit at the heart of nearly every embedded system, from industrial sensor nodes to consumer appliances, forming the lowest tier of the compute hierarchy alongside microprocessors, DSPs, and SoCs.
Key features of the LPC1317FBD64,551 include a 3-stage pipelined Cortex-M3 core with Harvard architecture (separate instruction/data buses plus a peripheral bus), USB device support, multiple USART ports, on-chip EEPROM, and the NXP MCU peripheral family. The device targets entry-level 32-bit applications where deterministic real-time behaviour, code density, and ease of use via the Cortex Microcontroller Software Interface Standard (CMSIS) are required.
The 72 MHz Cortex-M3 core provides 1.25 DMIPS/MHz (Dhrystone 2.1) performance, which is ample for protocol stacks, motor-control inner loops, and human-machine interface logic. The Harvard bus structure enables simultaneous fetches on the instruction and data paths, reducing stalls. Integrated EEPROM provides byte-erasable non-volatile storage for configuration or calibration records without external parts.
Typical applications include USB HID peripherals, industrial sensors, low-cost consumer devices, building automation, USB-to-UART bridges, and small motor-control subsystems. The combination of USB device plus USART plus GPIO makes it well suited as a flexible communications co-processor on larger boards.
When designing with the LPC1317FBD64,551, decouple VDD/VDDA with 100 nF ceramic capacitors placed close to each pin pair, and route the analog supply through a ferrite bead if the ADC is used. Confirm that the chosen crystal or internal oscillator setting matches the USB baud derivation tree when USB device operation is required.
This page synthesizes distributor pricing, drop-in alternative MPNs, and practical design notes that complement the NXP datasheet and standard distributor listings.
直接替换替代料： LPC1317FBD64,551 ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
快速对比工具——选择替代料号进行并排对比：
LPC1347FBD64,551
✅ 直接替换 ⚠️ 规格未核验📋 参考替代料（不在目录中）
LPC1315FBD64,551
✅ 直接替换 ⚠️ 规格未核验📋 参考替代料（不在目录中）
LPC1313FBD64,551
✅ 直接替换 ⚠️ 规格未核验📋 参考替代料（不在目录中）
LPC1343FBD64,551
✅ 直接替换 ⚠️ 规格未核验📋 参考替代料（不在目录中）
LPC1317FBD64,551 最大额定值与电气特性
| Core | ARM Cortex-M3 |
| 数据总线宽度 | 32 bit |
| 最大时钟频率 | 72 MHz |
| Program Memory Size | 64 KB (64K x 8) FLASH |
| RAM Size | 12 KB SRAM |
| EEPROM | On-chip |
| 封装 | 64-LQFP (10x10 mm) |
| 安装类型 | Surface Mount |
| USB | USB Device |
| USART | Yes (multiple instances) |
| RoHS 状态 | Compliant |
| CPU Architecture | Harvard, 3-stage pipeline |
LPC1317FBD64,551 引脚配置
| 引脚 1 | P1_0 — GPIO / Wake-up |
| 引脚 2 | P1_1 — GPIO |
| 引脚 3 | P1_2 — GPIO |
| 引脚 4 | P1_3 — GPIO |
| 引脚 5 | P1_4 — GPIO |
| 引脚 6 | P1_5 — GPIO |
| 引脚 7 | P1_6 — GPIO |
| 引脚 8 | P1_7 — GPIO |
| 引脚 9 | P1_8 — GPIO |
| 引脚 10 | P1_9 — GPIO |
| 引脚 11 | VDD — Power supply |
| 引脚 12 | VSS — Ground |
| 引脚 13 | XTAL1 — Crystal oscillator input |
| 引脚 14 | XTAL2 — Crystal oscillator output |
| 引脚 15 | RST — Reset (active low) |
| 引脚 16 | P2_0 — GPIO |
| 引脚 17 | P2_1 — GPIO |
| 引脚 18 | P2_2 — GPIO |
| 引脚 19 | P2_3 — GPIO |
| 引脚 20 | P2_4 — GPIO |
| 引脚 21 | P2_5 — GPIO |
| 引脚 22 | P2_6 — GPIO |
| 引脚 23 | P2_7 — GPIO |
| 引脚 24 | P2_8 — GPIO |
| 引脚 25 | P2_9 — GPIO |
| 引脚 26 | P2_10 — GPIO |
| 引脚 27 | P2_11 — GPIO |
| 引脚 28 | P2_12 — GPIO |
| 引脚 29 | P2_13 — GPIO |
| 引脚 30 | VDD — Power supply |
| 引脚 31 | VSS — Ground |
| 引脚 32 | P3_0 — GPIO |
| 引脚 33 | P3_1 — GPIO |
| 引脚 34 | P3_2 — GPIO / INT0 |
| 引脚 35 | P3_3 — GPIO / INT1 |
| 引脚 36 | P3_4 — GPIO |
| 引脚 37 | P3_5 — GPIO |
| 引脚 38 | P3_6 — GPIO |
| 引脚 39 | P3_7 — GPIO |
| 引脚 40 | P3_8 — GPIO |
| 引脚 41 | P3_9 — GPIO |
| 引脚 42 | P3_10 — GPIO |
| 引脚 43 | P3_11 — GPIO |
| 引脚 44 | P3_12 — GPIO |
| 引脚 45 | P3_13 — GPIO |
| 引脚 46 | P3_14 — GPIO |
| 引脚 47 | VSS — Ground |
| 引脚 48 | VDD — Power supply |
| 引脚 49 | P0_0 — GPIO / ADC0 |
| 引脚 50 | P0_1 — GPIO / ADC1 |
| 引脚 51 | P0_2 — GPIO / ADC2 |
| 引脚 52 | P0_3 — GPIO / ADC3 |
| 引脚 53 | P0_4 — GPIO / ADC4 / SDA |
| 引脚 54 | P0_5 — GPIO / ADC5 / SCL |
| 引脚 55 | P0_6 — GPIO |
| 引脚 56 | P0_7 — GPIO |
| 引脚 57 | P0_8 — GPIO / USB_VBUS |
| 引脚 58 | P0_9 — GPIO / USB_CONNECT |
| 引脚 59 | P0_10 — GPIO / USB_DM |
| 引脚 60 | P0_11 — GPIO / USB_DP |
| 引脚 61 | P0_12 — GPIO |
| 引脚 62 | P0_13 — GPIO |
| 引脚 63 | P1_10 — GPIO |
| 引脚 64 | P1_11 — GPIO |
典型应用
LPC1317FBD64,551 适用于 7 应用s: USB HID Peripheral Devices, Industrial Sensor Nodes, Building Automation Controllers, USB-to-UART Bridge Modules, Small Motor Control Subsystems, Low-Cost Consumer Devices, Communication Co-Processor.
USB HID Peripheral Devices
The LPC1317FBD64,551 fits USB HID peripherals because its on-chip USB 2.0 full-speed Device controller, 72 MHz Cortex-M3 core, and 64 KB flash cover the firmware size and protocol stack needs of typical HID keyboards, mice, game controllers, and custom-interface devices. The 1.25 DMIPS/MHz headroom handles HID report parsing and debouncing without bottlenecks. Placed as the sole MCU with a USB connector and a 12 MHz crystal, the part also benefits from the on-chip USB bootloader that simplifies field firmware updates without an external programmer.
推荐
Industrial Sensor Nodes
The LPC1317FBD64,551 suits industrial sensor nodes because its 64 KB flash accommodates protocol stacks such as Modbus RTU, the 12 KB SRAM buffers measurement bursts, and the multiple USARTs enable simultaneous RS-485 and debug-port connections. The 72 MHz Cortex-M3 core handles periodic sampling at sub-millisecond rates while remaining within the industrial temperature range documented for the LPC13xx family. Place the MCU alongside an isolated RS-485 transceiver and a 4-20 mA sensor front-end; the on-chip EEPROM stores calibration coefficients without external parts.
推荐
Building Automation Controllers
The LPC1317FBD64,551 fits building automation controllers because its GPIO count, 64 KB flash, and USART peripherals support HVAC damper control, lighting keypads, and occupancy sensor hubs. The Cortex-M3 deterministic interrupt latency makes it suitable for time-sensitive control loops, while the on-chip EEPROM stores user configuration across power cycles. Pair with an isolated 24V-to-3.3V DC-DC and a triac driver stage; the MCU's GPIO slew rate is sufficient for direct low-side MOSFET drive at modest currents.
推荐
USB-to-UART Bridge Modules
The LPC1317FBD64,551 is well matched to USB-to-UART bridge modules because the USB Device controller plus multiple USARTs implement CDC-ACM bridges with no external PHY required. The 64 KB flash fits composite USB-CDC plus vendor-class firmware, and the 72 MHz core keeps UART throughput comfortably below the USB full-speed limit. A minimal BOM uses just the MCU, a 12 MHz crystal, and an ESD-protected USB connector; firmware from NXP USB CDC reference stacks accelerates time-to-market.
推荐
Small Motor Control Subsystems
The LPC1317FBD64,551 suits small brushed-DC and stepper motor subsystems because the Cortex-M3 72 MHz core runs trapezoidal commutation and basic PID loops with deterministic timing, while the GPIO and PWM timers drive H-bridge MOSFETs. The 64 KB flash fits state-machine plus speed-profile firmware, and the on-chip EEPROM holds calibrated current limits. Place the MCU adjacent to the gate driver; the GPIO slew rate is appropriate for logic-level MOSFETs at switching frequencies up to ~30 kHz.
推荐
Low-Cost Consumer Devices
The LPC1317FBD64,551 fits low-cost consumer devices such as remote controls, smart-home sensor hubs, and appliance user-interface boards because the integrated peripherals (USB, USART, GPIO, timers, ADC) eliminate external components and reduce BOM cost. The 64 KB flash covers connectivity stacks and application logic, while the Cortex-M3 core keeps responsiveness snappy under interrupt-driven user input. Combine with a low-dropout regulator and a small OLED or LED indicator; the MCU's GPIO directly drives common-chars displays at modest frame frequencies.
推荐
Communication Co-Processor
The LPC1317FBD64,551 works well as a communication co-processor on larger boards because its USB device, USARTs, and Cortex-M3 throughput offload protocol stacks from a host application processor. The 64 KB flash accommodates lightweight TCP/IP or proprietary RF-link glue code, and the GPIO can wake a host on incoming traffic. Place it adjacent to the host SoC with a UART or USB link; the on-chip EEPROM stores link credentials without an external memory part.
推荐
推荐产品汇总
工程参考数据： LPC1317FBD64,551 ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | LPC1347FBD64,551 | LPC1315FBD64,551 | LPC1313FBD64,551 | LPC1343FBD64,551 |
|---|---|---|---|---|---|
| Brand | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors |
| Package | 64-LQFP (10x10) | 64-LQFP (10x10) - same | 64-LQFP (10x10) - same | 64-LQFP (10x10) - same | 64-LQFP (10x10) - same |
| Core | ARM Cortex-M3 | ARM Cortex-M3 | ARM Cortex-M3 | ARM Cortex-M3 | ARM Cortex-M3 |
| Maximum Clock Frequency | 72 MHz | 72 MHz | 72 MHz | 72 MHz | 72 MHz |
| Flash Size | 64 KB | 64 KB | 32 KB | 24 KB | 32 KB |
| SRAM Size | 12 KB | 12 KB | 8 KB | 8 KB | 8 KB |
| USB | USB 2.0 Full-Speed Device | USB 2.0 FS Device + bootloader | USB 2.0 FS Device | USB 2.0 FS Device | USB 2.0 FS Device |
| EEPROM | Yes (on-chip) | Yes (on-chip) | Yes (on-chip) | Yes (on-chip) | Yes (on-chip) |
关键差异点
- Largest flash in LPC1317 64-LQFP family （对比 LPC1315FBD64,551)
- Integrated USB 2.0 full-speed Device controller （对比 LPC1313FBD64,551)
- On-chip EEPROM for parameter storage （对比 Generic Cortex-M0 64-LQFP MCU)
设计说明
Estimated: Decouple each VDD pin with a 100 nF X7R ceramic placed within 3 mm of the pin, and add a bulk 4.7 uF tantalum or ceramic near the package. The LPC1317FBD64,551 operates from a single 3.3 V supply rail; verify the absolute maximum VDD from the datasheet before applying 5 V to any GPIO. Sequence the analog and digital rails together if ADC accuracy matters.
Keep the 12 MHz crystal traces short and symmetric, with a guard ground pour to reduce EMI injection into the USB DP/DM pair. Route USB differential lines with 90 ohm differential impedance and place the ESD protection array close to the connector. Place the MCU's VSS pin via directly under the exposed pad (LQFP-64 does not have an exposed pad; use multiple through-vias to inner ground planes).
Do not enable the USB peripheral until the PLL is locked and the 48 MHz USB clock is stable, otherwise the host will enumerate failures. Confirm that the ISP entry pins are not pulled low at reset if you want the user application to run immediately. Verify unused GPIO are configured as outputs or inputs with the internal pull-up enabled to avoid floating-pin current draw.
合规信息
RoHS and REACH compliance per NXP product page. Not AEC-Q100 qualified - this part targets industrial and consumer applications.