LTC2122IUK - Dual 14-Bit 170Msps ADC w/ JESD204B | ADI
MPN: LTC2122IUK ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $102.5 | $102.50 |
| 10 | $95.36 | $953.60 |
| 100 | $89.2 | $8,920.00 |
| 500 | $85.1 | $42,550.00 |
| 1,000 | $81.5 | $81,500.00 |
LTC2122IUK Overview
A pipelined ADC architecture uses a high-speed, multi-stage switched-capacitor structure with digital error correction, allowing the LTC2122 to maintain 14-bit linearity up to 170 Msps. Dual-channel simultaneous sampling eliminates inter-channel skew, critical for MIMO receivers, phased-array radar, and diversity antenna systems. The JESD204B serial interface transports the digitized data using up to 4 lanes with 8b/10b encoding, deterministic latency, and embedded clock recovery, which minimizes board routing complexity compared to LVDS parallel interfaces. An on-chip SYSREF input supports deterministic latency for multi-device synchronization in large-channel-count systems.
The LTC2122 targets demanding communications applications including LTE and multi-carrier GSM base-station receivers, software-defined radio, cable infrastructure head-end digitization, and high-density MIMO systems. Its 70 dBFS SNR and 90 dBFS SFDR at 170 Msps enable the receiver to digitize a 60 MHz LTE carrier with margin for adjacent-channel blocker rejection. The 1.25 GHz input bandwidth also supports undersampling of L-band and S-band signals, reducing the number of downconversion stages in the signal chain. The 48-QFN (7x7) exposed-pad package provides a low thermal resistance path, allowing operation across the industrial -40C to +85C temperature range without derating at the rated sample rate.
For PCB layout, place 0.1uF and 10nF ceramic decoupling capacitors within 5 mm of each supply pin, with the exposed pad soldered to a continuous ground plane. Route the JESD204B serialized lanes as length-matched 100 ohm differential pairs with controlled 50 ohm single-ended impedance, and keep AC-coupled capacitors within 5 mm of the transmitter pins to meet the JESD204B eye-mask specification.
Drop-in alternatives for LTC2122IUK — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with LTC2122IUK (same form factor and footprint) — differing in RoHS Status.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
LTC2122CUK#PBF
✅ Drop-In📋 Reference alternative (not in catalog)
LTC2122IUK#PBF
✅ Drop-In📋 Reference alternative (not in catalog)
LTC2122IUK#TRPBF
✅ Drop-In📋 Reference alternative (not in catalog)
LTC2122IUK Maximum Ratings & Electrical Characteristics
| Resolution | 14 bit |
| Number of Channels | 2 (simultaneous sampling) |
| Sample Rate | 170 Msps |
| Architecture | Pipelined |
| Input Bandwidth | 1.25 GHz |
| SNR | 70 dBFS |
| SFDR | 90 dBFS |
| Digital Interface | JESD204B (subclass 1) |
| Number of JESD204B Lanes | Up to 4 |
| Analog Supply Voltage | 1.7 V to 1.9 V (1.8 V nominal) |
| Input Type | Differential |
| Operating Temperature | -40C to +85C (industrial) |
| Package | 48-QFN (7x7 mm) with exposed pad |
| Mounting Type | Surface Mount |
| RoHS Status | Compliant |
LTC2122IUK Pin Configuration
| Pin 1 | AIN+ — Channel A differential analog input positive |
| Pin 2 | AIN- — Channel A differential analog input negative |
| Pin 3 | VCM_A — Channel A common-mode voltage output |
| Pin 4 | GND — Analog ground |
| Pin 5 | VA — 1.8V analog supply |
| Pin 6 | GND — Analog ground |
| Pin 7 | VA — 1.8V analog supply |
| Pin 8 | GND — Analog ground |
| Pin 9 | ENC+ — Differential clock input positive |
| Pin 10 | ENC- — Differential clock input negative |
| Pin 11 | GND — Clock ground |
| Pin 12 | VA — 1.8V analog supply |
| Pin 13 | GND — Analog ground |
| Pin 14 | VA — 1.8V analog supply |
| Pin 15 | BIN- — Channel B differential analog input negative |
| Pin 16 | BIN+ — Channel B differential analog input positive |
| Pin 17 | VCM_B — Channel B common-mode voltage output |
| Pin 18 | GND — Analog ground |
| Pin 19 | VA — 1.8V analog supply |
| Pin 20 | GND — Analog ground |
| Pin 21 | VD — Digital supply |
| Pin 22 | GND — Digital ground |
| Pin 23 | VD — Digital supply |
| Pin 24 | GND — Digital ground |
| Pin 25 | DOUT0+ — JESD204B serial lane 0 positive |
| Pin 26 | DOUT0- — JESD204B serial lane 0 negative |
| Pin 27 | GND — Serializer ground |
| Pin 28 | DOUT1+ — JESD204B serial lane 1 positive |
| Pin 29 | DOUT1- — JESD204B serial lane 1 negative |
| Pin 30 | GND — Serializer ground |
| Pin 31 | DOUT2+ — JESD204B serial lane 2 positive |
| Pin 32 | DOUT2- — JESD204B serial lane 2 negative |
| Pin 33 | GND — Serializer ground |
| Pin 34 | DOUT3+ — JESD204B serial lane 3 positive |
| Pin 35 | DOUT3- — JESD204B serial lane 3 negative |
| Pin 36 | GND — Serializer ground |
| Pin 37 | SYREF+ — JESD204B SYSREF input positive |
| Pin 38 | SYREF- — JESD204B SYSREF input negative |
| Pin 39 | GND — Digital ground |
| Pin 40 | SCK — Serial configuration clock input |
| Pin 41 | SDI — Serial configuration data input |
| Pin 42 | SDO — Serial configuration data output |
| Pin 43 | CSN — Serial configuration chip select (active low) |
| Pin 44 | RESETN — Reset input (active low) |
| Pin 45 | PDN — Power down input (active high) |
| Pin 46 | GND — Digital ground |
| Pin 47 | VD — Digital supply |
| Pin 48 | GND — Digital ground |
| Pin 49 | EPAD — Exposed pad - thermal and ground (must be soldered to PCB ground plane) |
Typical Applications
LTC2122IUK is suitable for 6 applications: LTE Multi-Carrier Base Station Receiver, Software Defined Radio (SDR) Platforms, Phased-Array Radar Signal Digitization, Cable Infrastructure Head-End Digitization, MIMO Wireless Test and Measurement, Medical Ultrasound Imaging Receivers.
LTE Multi-Carrier Base Station Receiver
The LTC2122IUK is ideally suited for LTE and multi-carrier GSM base-station receiver applications where dual-channel simultaneous sampling at 170 Msps is required. Its 70 dBFS SNR and 90 dBFS SFDR provide the dynamic range needed to digitize a 60 MHz LTE carrier with adjacent-channel blocker rejection margin, while the 1.25 GHz input bandwidth supports direct IF sampling of L-band signals. The JESD204B serial interface with SYSREF synchronization allows multiple LTC2122IUK devices to be ganged together for multi-sector or massive-MIMO antenna arrays, with deterministic latency simplifying baseband DSP timing. The dual simultaneous-sampling channels eliminate inter-channel skew for receiver diversity and beamforming applications, and the 48-QFN (7x7) exposed-pad package provides adequate thermal performance for continuous full-rate operation in densely populated base-station line cards.
Recommended
Software Defined Radio (SDR) Platforms
In wideband software-defined radio platforms, the LTC2122IUK digitizes I and Q baseband signals simultaneously at 170 Msps with 14-bit resolution. The dual-channel architecture maps directly to direct-conversion I/Q receiver front-ends, eliminating the need for separate baseband ADCs. The 1.25 GHz input bandwidth supports undersampling of HF, VHF, and UHF signals, allowing the SDR to cover multiple frequency bands with a single fixed anti-alias filter. The JESD204B interface connects the LTC2122IUK directly to FPGAs (Xilinx 7-series, Intel Cyclone V) with a small number of high-speed serial lanes, freeing board space for RF front-end components. The 70 dBFS SNR preserves signal-to-noise ratio for weak signal demodulation, while 90 dBFS SFDR prevents intermodulation distortion from degrading adjacent-channel reception.
Recommended
Phased-Array Radar Signal Digitization
The dual-channel simultaneous sampling and JESD204B SYSREF synchronization make the LTC2122IUK a strong fit for phased-array radar sub-array digitization. Each sub-array tile digitizes two antenna channels at 170 Msps, and multiple LTC2122IUK devices are time-aligned via the SYSREF input, providing deterministic sample-phase alignment across a 64-element or larger antenna array. The 1.25 GHz input bandwidth supports L-band and S-band radar IF sampling, and the 70 dBFS SNR preserves the dynamic range needed to detect small targets in clutter. The 48-QFN (7x7) package with exposed pad enables dense placement on radar tile boards, while the JESD204B interface transports sample data to a central FPGA beamformer over a few serial lanes. The industrial -40C to +85C temperature range supports outdoor military and aerospace radar installations.
Recommended
Cable Infrastructure Head-End Digitization
Cable television head-end equipment digitizes downstream QAM and OFDM channels directly at IF, and the LTC2122IUK's 170 Msps sample rate covers an 80 MHz upstream DOCSIS 3.1 channel block with margin. The 70 dBFS SNR and 90 dBFS SFDR support the carrier-to-noise and modulation-error-ratio requirements of 1024-QAM and 4096-QAM downstream modulation. The dual channels allow one LTC2122IUK to digitize both upstream and downstream spectrum segments simultaneously, reducing BOM cost per head-end channel. The 1.25 GHz input bandwidth supports direct sampling of L-band cable IF, and the JESD204B interface connects to cable modem termination system (CMTS) ASICs and FPGAs. The 48-QFN exposed-pad package handles the thermal load of continuous 170 Msps operation in enclosed head-end rack equipment.
Recommended
MIMO Wireless Test and Measurement
Wireless test and measurement instruments use the LTC2122IUK to digitize multiple antenna channels simultaneously for 4G/5G MIMO receiver test. The dual simultaneous-sampling channels allow a single LTC2122IUK to capture two streams of a 4x4 MIMO downlink, with matched gain and phase response between channels. The 170 Msps sample rate handles 100 MHz 5G NR signal bandwidth, and the 70 dBFS SNR supports EVM measurements down to -45 dB at the digitizer. The JESD204B interface streams samples to an FPGA-based real-time signal processor for EVM, ACLR, and spectral analysis. The 1.25 GHz input bandwidth supports over-the-air testing of millimeter-wave 5G systems after external downconversion, and the 48-QFN (7x7) package provides 2-channel density in compact production test rack form factors.
Recommended
Medical Ultrasound Imaging Receivers
Medical ultrasound imaging systems use the LTC2122IUK to digitize the I and Q quadrature outputs of the receive beamformer, with 14-bit resolution and 170 Msps sample rate supporting high-frequency linear and phased-array probes. The dual simultaneous-sampling channels reduce the channel-to-channel timing skew that would otherwise degrade beamforming resolution, and the 70 dBFS SNR preserves the dynamic range needed to visualize small tissue structures. The JESD204B interface transports the digitized RF data to a beamforming FPGA over a small number of serial lanes, reducing PCB density in 64-channel and 128-channel ultrasound carts. The 1.25 GHz input bandwidth supports up to 50 MHz probe frequency with harmonic imaging, and the 48-QFN (7x7) package enables compact portable ultrasound designs.
Recommended
Recommended Products Summary
Engineering reference data for LTC2122IUK — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | LTC2122CUK#PBF | LTC2122IUK#PBF | LTC2122IUK#TRPBF |
|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | 48-QFN (7x7) | 48-QFN (7x7) - same | 48-QFN (7x7) - same | 48-QFN (7x7) - same |
| Resolution | 14 bit | 14 bit | 14 bit | 14 bit |
| Sample Rate | 170 Msps | 170 Msps | 170 Msps | 170 Msps |
| Number of Channels | 2 (simultaneous) | 2 (simultaneous) | 2 (simultaneous) | 2 (simultaneous) |
| Interface | JESD204B (4 lanes) | JESD204B (4 lanes) | JESD204B (4 lanes) | JESD204B (4 lanes) |
| SNR | 70 dBFS | 70 dBFS | 70 dBFS | 70 dBFS |
| Operating Temperature | -40C to +85C | 0C to +70C (commercial) | -40C to +85C (industrial) | -40C to +85C (industrial) |
| Ordering Code Suffix | IUK (industrial grade) | CUK#PBF (commercial, Pb-free) | IUK#PBF (industrial, Pb-free) | IUK#TRPBF (industrial, Pb-free, T&R) |
Key Differentiators
- Industrial temperature grade for harsh environments (vs LTC2122CUK#PBF)
- Lead-free (Pb-free) ordering code with identical performance (vs LTC2122IUK (base MPN))
- Tape-and-reel packaging for high-volume production (vs LTC2122IUK#PBF (tray))
Design Notes
Place 0.1uF and 10nF ceramic decoupling capacitors within 5 mm of each VA and VD supply pin. The exposed pad (pin 49) must be soldered to a continuous ground plane to provide the low thermal resistance path specified in the datasheet. Without proper exposed-pad soldering, junction temperature can rise and degrade AC performance. The JESD204B serial data lanes should be routed as 100 ohm differential pairs with length matching within 0.5 mm to maintain lane-to-lane skew compliance.
Keep the differential analog inputs (AIN+/AIN-, BIN+/BIN-) as short as possible, with controlled 100 ohm differential impedance. Place the input common-mode bypass capacitor (typically 0.1uF) within 5 mm of the VCM_A and VCM_B pins. Separate the analog input traces from the JESD204B digital output traces to minimize digital noise coupling into the analog front-end. Use a ground cutout beneath the input balun network if used, to reduce parasitic capacitance.
Do not exceed the maximum analog supply voltage of 1.9V - the LTC2122 is not 3.3V tolerant. Ensure the ENC+/ENC- differential clock meets the JESD204B input clock specification (typically 0.5V to 1.5Vpp differential) - an improper clock amplitude will cause sub-optimal SNR and SFDR. After power-up, the RESETN pin must be held low for at least 1us before being released, to ensure proper initialization of the digital logic and JESD204B serializer.
Compliance Information
RoHS compliant per Analog Devices product page. Pb-free manufacturing indicated by #PBF suffix. Not AEC-Q100 qualified - this part targets communications and instrumentation, not automotive.