LTC2122IUK - Dual 14-Bit 170Msps ADC w/ JESD204B | ADI
料号： LTC2122IUK ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $102.5 | $102.50 |
| 10 | $95.36 | $953.60 |
| 100 | $89.2 | $8,920.00 |
| 500 | $85.1 | $42,550.00 |
| 1,000 | $81.5 | $81,500.00 |
LTC2122IUK 概述
A pipelined ADC architecture uses a high-speed, multi-stage switched-capacitor structure with digital error correction, allowing the LTC2122 to maintain 14-bit linearity up to 170 Msps. Dual-channel simultaneous sampling eliminates inter-channel skew, critical for MIMO receivers, phased-array radar, and diversity antenna systems. The JESD204B serial interface transports the digitized data using up to 4 lanes with 8b/10b encoding, deterministic latency, and embedded clock recovery, which minimizes board routing complexity compared to LVDS parallel interfaces. An on-chip SYSREF input supports deterministic latency for multi-device synchronization in large-channel-count systems.
The LTC2122 targets demanding communications applications including LTE and multi-carrier GSM base-station receivers, software-defined radio, cable infrastructure head-end digitization, and high-density MIMO systems. Its 70 dBFS SNR and 90 dBFS SFDR at 170 Msps enable the receiver to digitize a 60 MHz LTE carrier with margin for adjacent-channel blocker rejection. The 1.25 GHz input bandwidth also supports undersampling of L-band and S-band signals, reducing the number of downconversion stages in the signal chain. The 48-QFN (7x7) exposed-pad package provides a low thermal resistance path, allowing operation across the industrial -40C to +85C temperature range without derating at the rated sample rate.
For PCB layout, place 0.1uF and 10nF ceramic decoupling capacitors within 5 mm of each supply pin, with the exposed pad soldered to a continuous ground plane. Route the JESD204B serialized lanes as length-matched 100 ohm differential pairs with controlled 50 ohm single-ended impedance, and keep AC-coupled capacitors within 5 mm of the transmitter pins to meet the JESD204B eye-mask specification.
直接替换替代料： LTC2122IUK ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： LTC2122IUK （相同外形与封装尺寸） ——差异在于 RoHS Status.
快速对比工具——选择替代料号进行并排对比：
LTC2122CUK#PBF
✅ 直接替换📋 参考替代料（不在目录中）
LTC2122IUK#PBF
✅ 直接替换📋 参考替代料（不在目录中）
LTC2122IUK#TRPBF
✅ 直接替换📋 参考替代料（不在目录中）
LTC2122IUK 最大额定值与电气特性
| 分辨率 | 14 bit |
| Number of Channels | 2 (simultaneous sampling) |
| Sample Rate | 170 Msps |
| Architecture | Pipelined |
| Input Bandwidth | 1.25 GHz |
| SNR | 70 dBFS |
| SFDR | 90 dBFS |
| Digital Interface | JESD204B (subclass 1) |
| Number of JESD204B Lanes | Up to 4 |
| Analog Supply Voltage | 1.7 V to 1.9 V (1.8 V nominal) |
| Input Type | Differential |
| 工作温度 | -40C to +85C (industrial) |
| 封装 | 48-QFN (7x7 mm) with exposed pad |
| 安装类型 | Surface Mount |
| RoHS 状态 | Compliant |
LTC2122IUK 引脚配置
| 引脚 1 | AIN+ — Channel A differential analog input positive |
| 引脚 2 | AIN- — Channel A differential analog input negative |
| 引脚 3 | VCM_A — Channel A common-mode voltage output |
| 引脚 4 | GND — Analog ground |
| 引脚 5 | VA — 1.8V analog supply |
| 引脚 6 | GND — Analog ground |
| 引脚 7 | VA — 1.8V analog supply |
| 引脚 8 | GND — Analog ground |
| 引脚 9 | ENC+ — Differential clock input positive |
| 引脚 10 | ENC- — Differential clock input negative |
| 引脚 11 | GND — Clock ground |
| 引脚 12 | VA — 1.8V analog supply |
| 引脚 13 | GND — Analog ground |
| 引脚 14 | VA — 1.8V analog supply |
| 引脚 15 | BIN- — Channel B differential analog input negative |
| 引脚 16 | BIN+ — Channel B differential analog input positive |
| 引脚 17 | VCM_B — Channel B common-mode voltage output |
| 引脚 18 | GND — Analog ground |
| 引脚 19 | VA — 1.8V analog supply |
| 引脚 20 | GND — Analog ground |
| 引脚 21 | VD — Digital supply |
| 引脚 22 | GND — Digital ground |
| 引脚 23 | VD — Digital supply |
| 引脚 24 | GND — Digital ground |
| 引脚 25 | DOUT0+ — JESD204B serial lane 0 positive |
| 引脚 26 | DOUT0- — JESD204B serial lane 0 negative |
| 引脚 27 | GND — Serializer ground |
| 引脚 28 | DOUT1+ — JESD204B serial lane 1 positive |
| 引脚 29 | DOUT1- — JESD204B serial lane 1 negative |
| 引脚 30 | GND — Serializer ground |
| 引脚 31 | DOUT2+ — JESD204B serial lane 2 positive |
| 引脚 32 | DOUT2- — JESD204B serial lane 2 negative |
| 引脚 33 | GND — Serializer ground |
| 引脚 34 | DOUT3+ — JESD204B serial lane 3 positive |
| 引脚 35 | DOUT3- — JESD204B serial lane 3 negative |
| 引脚 36 | GND — Serializer ground |
| 引脚 37 | SYREF+ — JESD204B SYSREF input positive |
| 引脚 38 | SYREF- — JESD204B SYSREF input negative |
| 引脚 39 | GND — Digital ground |
| 引脚 40 | SCK — Serial configuration clock input |
| 引脚 41 | SDI — Serial configuration data input |
| 引脚 42 | SDO — Serial configuration data output |
| 引脚 43 | CSN — Serial configuration chip select (active low) |
| 引脚 44 | RESETN — Reset input (active low) |
| 引脚 45 | PDN — Power down input (active high) |
| 引脚 46 | GND — Digital ground |
| 引脚 47 | VD — Digital supply |
| 引脚 48 | GND — Digital ground |
| 引脚 49 | EPAD — Exposed pad - thermal and ground (must be soldered to PCB ground plane) |
典型应用
LTC2122IUK 适用于 6 应用s: LTE Multi-Carrier Base Station Receiver, Software Defined Radio (SDR) Platforms, Phased-Array Radar Signal Digitization, Cable Infrastructure Head-End Digitization, MIMO Wireless Test and Measurement, Medical Ultrasound Imaging Receivers.
LTE Multi-Carrier Base Station Receiver
The LTC2122IUK is ideally suited for LTE and multi-carrier GSM base-station receiver applications where dual-channel simultaneous sampling at 170 Msps is required. Its 70 dBFS SNR and 90 dBFS SFDR provide the dynamic range needed to digitize a 60 MHz LTE carrier with adjacent-channel blocker rejection margin, while the 1.25 GHz input bandwidth supports direct IF sampling of L-band signals. The JESD204B serial interface with SYSREF synchronization allows multiple LTC2122IUK devices to be ganged together for multi-sector or massive-MIMO antenna arrays, with deterministic latency simplifying baseband DSP timing. The dual simultaneous-sampling channels eliminate inter-channel skew for receiver diversity and beamforming applications, and the 48-QFN (7x7) exposed-pad package provides adequate thermal performance for continuous full-rate operation in densely populated base-station line cards.
推荐
Software Defined Radio (SDR) Platforms
In wideband software-defined radio platforms, the LTC2122IUK digitizes I and Q baseband signals simultaneously at 170 Msps with 14-bit resolution. The dual-channel architecture maps directly to direct-conversion I/Q receiver front-ends, eliminating the need for separate baseband ADCs. The 1.25 GHz input bandwidth supports undersampling of HF, VHF, and UHF signals, allowing the SDR to cover multiple frequency bands with a single fixed anti-alias filter. The JESD204B interface connects the LTC2122IUK directly to FPGAs (Xilinx 7-series, Intel Cyclone V) with a small number of high-speed serial lanes, freeing board space for RF front-end components. The 70 dBFS SNR preserves signal-to-noise ratio for weak signal demodulation, while 90 dBFS SFDR prevents intermodulation distortion from degrading adjacent-channel reception.
推荐
Phased-Array Radar Signal Digitization
The dual-channel simultaneous sampling and JESD204B SYSREF synchronization make the LTC2122IUK a strong fit for phased-array radar sub-array digitization. Each sub-array tile digitizes two antenna channels at 170 Msps, and multiple LTC2122IUK devices are time-aligned via the SYSREF input, providing deterministic sample-phase alignment across a 64-element or larger antenna array. The 1.25 GHz input bandwidth supports L-band and S-band radar IF sampling, and the 70 dBFS SNR preserves the dynamic range needed to detect small targets in clutter. The 48-QFN (7x7) package with exposed pad enables dense placement on radar tile boards, while the JESD204B interface transports sample data to a central FPGA beamformer over a few serial lanes. The industrial -40C to +85C temperature range supports outdoor military and aerospace radar installations.
推荐
Cable Infrastructure Head-End Digitization
Cable television head-end equipment digitizes downstream QAM and OFDM channels directly at IF, and the LTC2122IUK's 170 Msps sample rate covers an 80 MHz upstream DOCSIS 3.1 channel block with margin. The 70 dBFS SNR and 90 dBFS SFDR support the carrier-to-noise and modulation-error-ratio requirements of 1024-QAM and 4096-QAM downstream modulation. The dual channels allow one LTC2122IUK to digitize both upstream and downstream spectrum segments simultaneously, reducing BOM cost per head-end channel. The 1.25 GHz input bandwidth supports direct sampling of L-band cable IF, and the JESD204B interface connects to cable modem termination system (CMTS) ASICs and FPGAs. The 48-QFN exposed-pad package handles the thermal load of continuous 170 Msps operation in enclosed head-end rack equipment.
推荐
MIMO Wireless Test and Measurement
Wireless test and measurement instruments use the LTC2122IUK to digitize multiple antenna channels simultaneously for 4G/5G MIMO receiver test. The dual simultaneous-sampling channels allow a single LTC2122IUK to capture two streams of a 4x4 MIMO downlink, with matched gain and phase response between channels. The 170 Msps sample rate handles 100 MHz 5G NR signal bandwidth, and the 70 dBFS SNR supports EVM measurements down to -45 dB at the digitizer. The JESD204B interface streams samples to an FPGA-based real-time signal processor for EVM, ACLR, and spectral analysis. The 1.25 GHz input bandwidth supports over-the-air testing of millimeter-wave 5G systems after external downconversion, and the 48-QFN (7x7) package provides 2-channel density in compact production test rack form factors.
推荐
Medical Ultrasound Imaging Receivers
Medical ultrasound imaging systems use the LTC2122IUK to digitize the I and Q quadrature outputs of the receive beamformer, with 14-bit resolution and 170 Msps sample rate supporting high-frequency linear and phased-array probes. The dual simultaneous-sampling channels reduce the channel-to-channel timing skew that would otherwise degrade beamforming resolution, and the 70 dBFS SNR preserves the dynamic range needed to visualize small tissue structures. The JESD204B interface transports the digitized RF data to a beamforming FPGA over a small number of serial lanes, reducing PCB density in 64-channel and 128-channel ultrasound carts. The 1.25 GHz input bandwidth supports up to 50 MHz probe frequency with harmonic imaging, and the 48-QFN (7x7) package enables compact portable ultrasound designs.
推荐
推荐产品汇总
工程参考数据： LTC2122IUK ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | LTC2122CUK#PBF | LTC2122IUK#PBF | LTC2122IUK#TRPBF |
|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | 48-QFN (7x7) | 48-QFN (7x7) - same | 48-QFN (7x7) - same | 48-QFN (7x7) - same |
| Resolution | 14 bit | 14 bit | 14 bit | 14 bit |
| Sample Rate | 170 Msps | 170 Msps | 170 Msps | 170 Msps |
| Number of Channels | 2 (simultaneous) | 2 (simultaneous) | 2 (simultaneous) | 2 (simultaneous) |
| Interface | JESD204B (4 lanes) | JESD204B (4 lanes) | JESD204B (4 lanes) | JESD204B (4 lanes) |
| SNR | 70 dBFS | 70 dBFS | 70 dBFS | 70 dBFS |
| Operating Temperature | -40C to +85C | 0C to +70C (commercial) | -40C to +85C (industrial) | -40C to +85C (industrial) |
| Ordering Code Suffix | IUK (industrial grade) | CUK#PBF (commercial, Pb-free) | IUK#PBF (industrial, Pb-free) | IUK#TRPBF (industrial, Pb-free, T&R) |
关键差异点
- Industrial temperature grade for harsh environments （对比 LTC2122CUK#PBF)
- Lead-free (Pb-free) ordering code with identical performance （对比 LTC2122IUK (base MPN))
- Tape-and-reel packaging for high-volume production （对比 LTC2122IUK#PBF (tray))
设计说明
Place 0.1uF and 10nF ceramic decoupling capacitors within 5 mm of each VA and VD supply pin. The exposed pad (pin 49) must be soldered to a continuous ground plane to provide the low thermal resistance path specified in the datasheet. Without proper exposed-pad soldering, junction temperature can rise and degrade AC performance. The JESD204B serial data lanes should be routed as 100 ohm differential pairs with length matching within 0.5 mm to maintain lane-to-lane skew compliance.
Keep the differential analog inputs (AIN+/AIN-, BIN+/BIN-) as short as possible, with controlled 100 ohm differential impedance. Place the input common-mode bypass capacitor (typically 0.1uF) within 5 mm of the VCM_A and VCM_B pins. Separate the analog input traces from the JESD204B digital output traces to minimize digital noise coupling into the analog front-end. Use a ground cutout beneath the input balun network if used, to reduce parasitic capacitance.
Do not exceed the maximum analog supply voltage of 1.9V - the LTC2122 is not 3.3V tolerant. Ensure the ENC+/ENC- differential clock meets the JESD204B input clock specification (typically 0.5V to 1.5Vpp differential) - an improper clock amplitude will cause sub-optimal SNR and SFDR. After power-up, the RESETN pin must be held low for at least 1us before being released, to ensure proper initialization of the digital logic and JESD204B serializer.
合规信息
RoHS compliant per Analog Devices product page. Pb-free manufacturing indicated by #PBF suffix. Not AEC-Q100 qualified - this part targets communications and instrumentation, not automotive.