LTC2240IUP-12 - 12-Bit 170Msps ADC, 64-QFN | Analog Devices
MPN: LTC2240IUP-12 ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $42.5 | $42.50 |
| 10 | $38.2 | $382.00 |
| 100 | $33.95 | $3,395.00 |
| 500 | $29.1 | $14,550.00 |
| 1,000 | $25.4 | $25,400.00 |
LTC2240IUP-12 Overview
An ADC (analog-to-digital converter) is a mixed-signal integrated circuit that converts real-world analog voltages into discrete digital codes at a sampling rate, serving as the interface between RF/analog front ends and digital signal processors. Within the broader signal-chain taxonomy, the LTC2240IUP-12 sits in the high-speed pipeline ADC category (12-bit resolution, 100+ Msps), which sits under successive-approximation and flash architectures for sampling rates up to several hundred Msps. In the system hierarchy, pipeline ADCs occupy the tier between general-purpose SAR ADCs (<=10 Msps) and ultra-high-speed interleaved or JESD204B-class ADCs (>500 Msps).
Key features of the LTC2240IUP-12 include a 65.6 dB signal-to-noise ratio, 80 dB SFDR at 170 Msps with a 70 MHz input, and an aperture jitter of 0.15 ps RMS, making it suitable for undersampling IF signals in communications receivers. The device supports full-power analog input bandwidth above 500 MHz and offers programmable gain and offset adjustment via dedicated SPI pins, with an internal bandgap reference and integrated input common-mode bias. Power dissipation is 638 mW typical at 170 Msps with CMOS outputs and scales downward at lower clock rates.
The LTC2240IUP-12 uses a multi-stage pipelined architecture with proprietary input sample-and-hold and digital error correction, allowing it to maintain 12-bit linearity and low spurious content across Nyquist input frequencies. The differential input structure provides common-mode rejection, and the LVDS output option enables high-data-rate transfer over long PCB traces without EMI issues. An internal duty-cycle stabilizer compensates for clock-source non-50 percent duty cycle, simplifying clock-tree design in FPGA-based systems.
Typical applications include cellular base-station receiver IF digitizers, cable-headend downstream QAM demodulators, radar and phased-array signal acquisition, medical imaging front ends, and high-speed data-acquisition cards for test and measurement. It also fits spectrum analyzer and software-defined radio ADC positions where 12-bit dynamic range at 170 Msps is sufficient.
When designing with this ADC, pay close attention to analog input network design: use a transformer-coupled or differential op-amp driver with appropriate input common-mode biasing, and provide a low-noise clock source with jitter below 0.5 ps RMS to preserve SNR. The exposed pad of the 64-QFN must be soldered to a continuous ground plane to achieve the rated thermal performance and to provide the necessary ground return for the input stage.
This page synthesizes distributor pricing, drop-in alternative MPNs, and practical design guidance that complement the official Analog Devices datasheet for procurement and engineering decisions.
Drop-in alternatives for LTC2240IUP-12 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with LTC2240IUP-12 (same form factor and footprint) — differing in Package, SFDR, SNR, Sample Rate, Aperture Jitter.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
LTC2240IUP-10
✅ Drop-In✓ In Stock
$18.75 / Unit
View Datasheet →LTC2240CUP-12
✅ Drop-In📋 Reference alternative (not in catalog)
LTC2241CUP-12
✅ Drop-In✓ In Stock
$30.1 / Unit
View Datasheet →LTC2221CUP
✅ Drop-In✓ In Stock
$34.2 / Unit
View Datasheet →LTC2206IUK
✅ Drop-In✓ In Stock
$24.95 / Unit
View Datasheet →LTC2240IUP-12 Maximum Ratings & Electrical Characteristics
| Resolution | 12 bits |
| Number of Channels | 1 |
| Sampling Rate | 170 Msps |
| Architecture | Pipelined |
| Input Type | Differential |
| Full-Scale Input Range | 2 Vp-p |
| Data Interface | Parallel CMOS or LVDS (selectable) |
| SNR | 65.6 dB at 70 MHz input |
| SFDR | 80 dB at 70 MHz input |
| Aperture Jitter | 0.15 ps RMS |
| Analog Supply Voltage | 3.3 V (typ) |
| Digital Supply Voltage | 3.3 V or 1.8 V (selectable) |
| Power Dissipation | 638 mW (typ, 170 Msps, CMOS outputs) |
| Package | 64-QFN (9x9 mm) with exposed pad |
| Operating Temperature Range (I grade) | -40 C to +85 C |
| Mounting Type | Surface Mount |
| RoHS Status | Compliant (#PBF suffix) |
LTC2240IUP-12 Pin Configuration
| Pin 1 | OGND — Output driver ground |
| Pin 2 | D0 — Data output bit 0 (LSB, CMOS or LVDS) |
| Pin 3 | D1 — Data output bit 1 (CMOS or LVDS) |
| Pin 4 | D2 — Data output bit 2 (CMOS or LVDS) |
| Pin 5 | D3 — Data output bit 3 (CMOS or LVDS) |
| Pin 6 | D4 — Data output bit 4 (CMOS or LVDS) |
| Pin 7 | D5 — Data output bit 5 (CMOS or LVDS) |
| Pin 8 | D6 — Data output bit 6 (CMOS or LVDS) |
| Pin 9 | D7 — Data output bit 7 (CMOS or LVDS) |
| Pin 10 | OGND — Output driver ground |
| Pin 11 | D8 — Data output bit 8 (CMOS or LVDS) |
| Pin 12 | D9 — Data output bit 9 (CMOS or LVDS) |
| Pin 13 | D10 — Data output bit 10 (CMOS or LVDS) |
| Pin 14 | D11 — Data output bit 11 (MSB, CMOS or LVDS) |
| Pin 15 | OGND — Output driver ground |
| Pin 16 | OVDD — Output driver supply |
| Pin 17 | OVDD — Output driver supply |
| Pin 18 | OGND — Output driver ground |
| Pin 19 | CLKOUT- — Differential clock output negative |
| Pin 20 | CLKOUT+ — Differential clock output positive |
| Pin 21 | OGND — Output driver ground |
| Pin 22 | ENC+ — Encode clock input positive |
| Pin 23 | ENC- — Encode clock input negative |
| Pin 24 | OGND — Output driver ground |
| Pin 25 | OVDD — Output driver supply |
| Pin 26 | OVDD — Output driver supply |
| Pin 27 | MODE — Output mode select (CMOS/LVDS) |
| Pin 28 | OGND — Output driver ground |
| Pin 29 | SHDN — Shutdown control (active high) |
| Pin 30 | CS — Chip select for serial configuration |
| Pin 31 | SCK — Serial configuration clock |
| Pin 32 | SDI — Serial configuration data input |
| Pin 33 | SDO — Serial configuration data output |
| Pin 34 | AGND — Analog ground |
| Pin 35 | VREF — Voltage reference bypass |
| Pin 36 | SENSE — Reference configuration pin |
| Pin 37 | VCM — Common-mode voltage output |
| Pin 38 | A+ — Differential analog input positive |
| Pin 39 | A- — Differential analog input negative |
| Pin 40 | AGND — Analog ground |
| Pin 41 | AGND — Analog ground |
| Pin 42 | AVDD — Analog 3.3V supply |
| Pin 43 | AVDD — Analog 3.3V supply |
| Pin 44 | AGND — Analog ground |
| Pin 45 | AGND — Analog ground |
| Pin 46 | AVDD — Analog 3.3V supply |
| Pin 47 | AVDD — Analog 3.3V supply |
| Pin 48 | AGND — Analog ground |
| Pin 49 | NC — Not connected (per datasheet) |
| Pin 50 | NC — Not connected (per datasheet) |
| Pin 51 | AGND — Analog ground |
| Pin 52 | AVDD — Analog 3.3V supply |
| Pin 53 | AVDD — Analog 3.3V supply |
| Pin 54 | AGND — Analog ground |
| Pin 55 | NC — Not connected (per datasheet) |
| Pin 56 | NC — Not connected (per datasheet) |
| Pin 57 | AGND — Analog ground |
| Pin 58 | AVDD — Analog 3.3V supply |
| Pin 59 | AVDD — Analog 3.3V supply |
| Pin 60 | AGND — Analog ground |
| Pin 61 | AGND — Analog ground |
| Pin 62 | AVDD — Analog 3.3V supply |
| Pin 63 | AVDD — Analog 3.3V supply |
| Pin 64 | AGND — Analog ground |
Typical Applications
LTC2240IUP-12 is suitable for 6 applications: Cellular Base-Station IF Digitizer, Cable Headend QAM Demodulator, Radar and Phased-Array Signal Acquisition, Medical Imaging Front End (Ultrasound), High-Speed Data Acquisition Card, Software-Defined Radio (SDR) Receiver.
Cellular Base-Station IF Digitizer
The LTC2240IUP-12 fits cellular base-station receiver IF digitizers because its 170 Msps sampling rate captures the full bandwidth of multi-carrier UMTS/LTE IF signals (typically 70-140 MHz) without aliasing. The 65.6 dB SNR and 80 dB SFDR preserve the noise figure and adjacent-channel rejection required for 3G/4G receiver sensitivity, and the LVDS output mode drives long PCB traces to the FPGA without EMI issues. Place the ADC after the final IF mixer and SAW filter; pair with a differential transformer driver (e.g., ADT1-1WT) and feed an FPGA with dedicated LVDS receivers. Unlike 16-bit ADCs in the same family, the LTC2240IUP-12 delivers sufficient dynamic range at lower power and cost for cost-sensitive pico-cell and femtocell deployments.
Recommended
Cable Headend QAM Demodulator
The LTC2240IUP-12 is suitable for cable-headend downstream QAM demodulation where the IF digitizer must capture a 6-8 MHz channel and several adjacent channels simultaneously. Its 170 Msps sampling rate and 80 dB SFDR provide enough spurious-free dynamic range to demodulate 256-QAM constellations without adjacent-channel interference artifacts; the differential input structure rejects common-mode noise from the upstream LNA. Use the ADC with an automatic gain control (AGC) loop ahead of the input transformer, and decode the LVDS outputs into a demodulator ASIC or FPGA running a soft-decision QAM algorithm. Compared with 14-bit ADCs, the LTC2240IUP-12 cuts cost while still delivering CNR margin for dense channel stacking.
Recommended
Radar and Phased-Array Signal Acquisition
The LTC2240IUP-12 works well in radar and phased-array receiver channels that require digitizing pulsed IF signals-Doppler returns. Its 0.15 ps RMS aperture jitter preserves SNR when sampling narrow pulse returns, and the 170 Msps rate captures the full radar IF bandwidth of 70-80 MHz without aliasing. The differential input accepts a transformer-coupled IF strip output, and the LVDS digital interface routes data cleanly to the FPGA or DSP back-end for matched-filter processing. For larger phased arrays requiring multiple ADC channels, several LTC2240IUP-12 devices share a common clock to maintain sample-accurate alignment across channels. Compared to 16-bit alternatives, the 12-bit resolution matches the dynamic range of most surveillance and weather radar front ends at lower cost and power.
Recommended
Medical Imaging Front End (Ultrasound)
The LTC2240IUP-12 can be used in portable ultrasound receiver boards where the IF stage output must be digitized at 40-70 MHz after the TGC (time-gain-compensation) amplifier. Its 65.6 dB SNR is sufficient for B-mode imaging dynamic range, and the 170 Msps rate captures the full IF passband needed for beamformer processing in the FPGA. The exposed-pad 64-QFN package provides the thermal relief required for dense multi-channel receiver boards where several ADCs sit adjacent to each other. Use a low-noise LDO for the analog supply rail and separate the digital LVDS traces from the analog input network with a continuous ground moat. Compared to higher-resolution ADCs, the LTC2240IUP-12 reduces per-channel cost for budget-constrained portable ultrasound designs.
Recommended
High-Speed Data Acquisition Card
The LTC2240IUP-12 fits PCI/PCIe data-acquisition cards for test and measurement instruments that sample one or two channels of transient or repetitive signals at high rates. The selectable CMOS or LVDS output modes let the card designer match the digital interface to the on-board FPGA or buffer memory; CMOS mode simplifies low-cost interfaces while LVDS supports high-data-rate streaming to a large FIFO bank. The single-channel input structure pairs naturally with an analog front-end multiplexer when multi-channel sampling is required. Compared to oscilloscope-grade ADCs, the LTC2240IUP-12 offers adequate 12-bit dynamic range at a far lower price per channel for production test equipment.
Recommended
Software-Defined Radio (SDR) Receiver
The LTC2240IUP-12 is a strong fit for software-defined radio receiver designs that digitize a low-IF or direct-conversion signal at 70-80 MHz. Its 0.15 ps aperture jitter is low enough to preserve SNR when undersampling higher-frequency tuners, and the 170 Msps rate delivers 80 MHz of usable Nyquist bandwidth for SDR channel aggregation. The LVDS output mode feeds an FPGA that performs channelization and demodulation in software, eliminating analog IF filter chains. Power dissipation of 638 mW is acceptable for fixed-install SDR receivers; for portable SDR applications, the lower-speed LTC2241CUP-12 reduces power while sharing the same footprint. Compared to JESD204B ADCs in higher-end SDR designs, the LTC2240IUP-12 simplifies board layout and FPGA firmware at the cost of more digital output traces.
Recommended
Recommended Products Summary
Engineering reference data for LTC2240IUP-12 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | LTC2240IUP-10 | LTC2240CUP-12 | LTC2241CUP-12 | LTC2221CUP | LTC2206IUK |
|---|---|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | 64-QFN (9x9) | 64-QFN (9x9) - same | 64-QFN (9x9) - same | 64-QFN (9x9) - same | 64-QFN (9x9) - same | 64-QFN (9x9) - same |
| Resolution | 12 bits | 10 bits | 12 bits | 12 bits | 12 bits | 16 bits |
| Sampling Rate | 170 Msps | 170 Msps | 170 Msps | 135 Msps | 105 Msps | 80 Msps |
| Temperature Grade | Industrial (-40 to +85 C) | Industrial (-40 to +85 C) | Commercial (0 to +70 C) | Commercial (0 to +70 C) | Commercial (0 to +70 C) | Industrial (-40 to +85 C) |
Key Differentiators
- Highest sampling rate in the LTC224x pin-compatible family (vs LTC2241CUP-12)
- Industrial temperature grade with 12-bit resolution (vs LTC2240IUP-10)
- Selectable CMOS or LVDS digital output in one device (vs LTC2206IUK)
Design Notes
Use a transformer-coupled or fully-differential op-amp driver at the analog input (A+, A-); a 1:1 transformer such as ADT1-1WT with 50 ohm termination on the primary side delivers the 2 Vp-p full-scale swing while providing common-mode rejection. Keep the analog input traces symmetric and short, and surround them with a continuous ground moat to avoid coupling from the LVDS digital outputs.
Aperture jitter is dominated by the encode clock source; use a low-jitter clock driver (e.g., a fixed-frequency TCXO or clean FPGA PLL output) with measured RMS jitter below 0.5 ps to preserve the rated 65.6 dB SNR. Running the encode clock through a noisy FPGA PLL or long distribution tree will degrade SNR by several dB. Route the encode clock differentially (ENC+/ENC-) and terminate at the ADC pins.
Estimated: at 638 mW typical dissipation in the 64-QFN package, junction temperature rise above ambient is approximately 33 C/W x 0.638 W = 21 C with the exposed pad soldered to a 1-square-inch copper ground plane on a 4-layer PCB. For densely-stacked multi-channel receiver boards, ensure each ADC has adequate copper area or consider airflow to keep junction temperature below 125 C.
Compliance Information
RoHS compliant as indicated by the #PBF suffix per Analog Devices product page. AEC-Q100 not applicable for this non-automotive-grade ADC. Halogen-free status not explicitly stated in verified web data.
