LTC2158CUP-14 - Dual 14-Bit 310Msps ADC | Analog Devices
MPN: LTC2158CUP-14 ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $65.4 | $65.40 |
| 10 | $58.9 | $589.00 |
| 100 | $52.1 | $5,210.00 |
| 500 | $46.85 | $23,425.00 |
| 1,000 | $41.2 | $41,200.00 |
LTC2158CUP-14 Overview
A pipelined ADC is a multi-step converter architecture that processes one conversion stage per clock cycle, allowing very high sample rates (hundreds of Msps to Gsps) while keeping per-stage comparator requirements modest. Within the broader signal-chain hierarchy, the LTC2158CUP-14 sits as an analog-to-digital converter -> data converter -> mixed-signal IC -> semiconductor. Its dual simultaneous-sampling channels make it a member of the high-speed pipeline-ADC family targeted at communications infrastructure, radar, and instrumentation.
Key features include dual simultaneous-sampling 14-bit 310 Msps conversion per channel, 68.8 dB SNR and 88 dB SFDR for wide dynamic-range capture, 1.25 GHz analog input bandwidth for IF sampling, 355 mA supply current from a 1.7 V to 1.9 V analog/digital supply, and an exposed-pad QFN-64 (9x9) package for low thermal resistance. The integrated input common-mode bias simplifies transformer or op-amp driver interfaces.
The device uses a multi-stage differential pipeline core with on-chip reference and sample-and-hold, supporting CMOS or DDR LVDS output formats for flexible FPGA/ASIC capture. LVDS outputs simplify board layout and reduce digital switching noise coupling into the analog front end.
Typical applications include communications receivers, cellular base-station digitizers, radar and phased-array signal processing, test and measurement instrumentation, and high-performance imaging. Dual simultaneous channels allow I/Q capture or diversity reception from a single converter IC.
When designing with the LTC2158CUP-14, decouple each analog and digital supply pin individually, route the LVDS outputs with 100 ohm differential impedance, and provide a low-jitter clock to CLK+ and CLK- to preserve SNR at full rate. The exposed pad must be soldered to a continuous ground plane for thermal dissipation and electrical reference.
This page synthesizes verified distributor pricing, drop-in QFN-64 same-family alternatives, and practical PCB/decoupling design notes not found in the manufacturer datasheet alone.
Drop-in alternatives for LTC2158CUP-14 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with LTC2158CUP-14 (same form factor and footprint) — differing in Package, Resolution, SNR, Operating Temperature Range, Sampling Rate.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
LTC2158IUP-14
✅ Drop-In📋 Reference alternative (not in catalog)
LTC2157CUP-14
✅ Drop-In✓ In Stock
$132.4 / Unit
View Datasheet →LTC2156IUP-14
✅ Drop-In✓ In Stock
$134.1 / Unit
View Datasheet →LTC2155CUP-12
✅ Drop-In✓ In Stock
$44.25 / Unit
View Datasheet →LTC2158CUP-14 Maximum Ratings & Electrical Characteristics
| Resolution | 14 bit |
| Number of Channels | 2 (simultaneous sampling) |
| Sampling Rate | 310 Msps per channel |
| Architecture | Pipelined |
| Input Bandwidth | 1.25 GHz |
| SNR | 68.8 dB |
| SFDR | 88 dB |
| Supply Current | 355 mA |
| Analog Supply Voltage | 1.7 V to 1.9 V |
| Digital Output Format | CMOS / DDR LVDS |
| Package | 64-QFN (9x9 mm) with exposed pad |
| Mounting Type | Surface Mount |
| Input Type | Differential |
| RoHS Status | Compliant (per #PBF suffix) |
LTC2158CUP-14 Pin Configuration
| Pin 1 | AIN1+ — Channel 1 differential analog input positive |
| Pin 2 | AIN1- — Channel 1 differential analog input negative |
| Pin 3 | VCM1 — Channel 1 common-mode voltage bias |
| Pin 4 | AGND — Analog ground |
| Pin 5 | AVDD — Analog supply (1.8 V nominal) |
| Pin 6 | AVDD — Analog supply (1.8 V nominal) |
| Pin 7 | REF — Reference voltage decoupling |
| Pin 8 | AGND — Analog ground |
| Pin 9 | SENSE — Reference mode select |
| Pin 10 | REFT — Top reference decoupling |
| Pin 11 | REFB — Bottom reference decoupling |
| Pin 12 | AGND — Analog ground |
| Pin 13 | AIN2+ — Channel 2 differential analog input positive |
| Pin 14 | AIN2- — Channel 2 differential analog input negative |
| Pin 15 | VCM2 — Channel 2 common-mode voltage bias |
| Pin 16 | AGND — Analog ground |
| Pin 17 | AVDD — Analog supply (1.8 V nominal) |
| Pin 18 | AVDD — Analog supply (1.8 V nominal) |
| Pin 19 | CLK+ — Differential clock input positive |
| Pin 20 | CLK- — Differential clock input negative |
| Pin 21 | AGND — Analog ground |
| Pin 22 | OGND — Output driver ground |
| Pin 23 | OVDD — Output driver supply (1.8 V nominal) |
| Pin 24 | OVDD — Output driver supply (1.8 V nominal) |
| Pin 25 | D0_1 — Channel 1 LVDS/CMOS output bit 0 (LSB) |
| Pin 26 | D1_1 — Channel 1 output bit 1 |
| Pin 27 | D2_1 — Channel 1 output bit 2 |
| Pin 28 | D3_1 — Channel 1 output bit 3 |
| Pin 29 | D4_1 — Channel 1 output bit 4 |
| Pin 30 | D5_1 — Channel 1 output bit 5 |
| Pin 31 | D6_1 — Channel 1 output bit 6 |
| Pin 32 | D7_1 — Channel 1 output bit 7 |
| Pin 33 | D8_1 — Channel 1 output bit 8 |
| Pin 34 | D9_1 — Channel 1 output bit 9 |
| Pin 35 | D10_1 — Channel 1 output bit 10 |
| Pin 36 | D11_1 — Channel 1 output bit 11 |
| Pin 37 | D12_1 — Channel 1 output bit 12 |
| Pin 38 | D13_1 — Channel 1 output bit 13 (MSB) |
| Pin 39 | DCLK1 — Channel 1 DDR clock output |
| Pin 40 | FR_N_1 — Channel 1 frame indicator (active low) |
| Pin 41 | OGND — Output driver ground |
| Pin 42 | OVDD — Output driver supply (1.8 V nominal) |
| Pin 43 | D0_2 — Channel 2 LVDS/CMOS output bit 0 (LSB) |
| Pin 44 | D1_2 — Channel 2 output bit 1 |
| Pin 45 | D2_2 — Channel 2 output bit 2 |
| Pin 46 | D3_2 — Channel 2 output bit 3 |
| Pin 47 | D4_2 — Channel 2 output bit 4 |
| Pin 48 | D5_2 — Channel 2 output bit 5 |
| Pin 49 | D6_2 — Channel 2 output bit 6 |
| Pin 50 | D7_2 — Channel 2 output bit 7 |
| Pin 51 | D8_2 — Channel 2 output bit 8 |
| Pin 52 | D9_2 — Channel 2 output bit 9 |
| Pin 53 | D10_2 — Channel 2 output bit 10 |
| Pin 54 | D11_2 — Channel 2 output bit 11 |
| Pin 55 | D12_2 — Channel 2 output bit 12 |
| Pin 56 | D13_2 — Channel 2 output bit 13 (MSB) |
| Pin 57 | DCLK2 — Channel 2 DDR clock output |
| Pin 58 | FR_N_2 — Channel 2 frame indicator (active low) |
| Pin 59 | OGND — Output driver ground |
| Pin 60 | OVDD — Output driver supply (1.8 V nominal) |
| Pin 61 | MODE — Output mode select (CMOS/LVDS) |
| Pin 62 | CS — Chip select / SPI enable |
| Pin 63 | SDI — SPI serial data input |
| Pin 64 | SCK — SPI serial clock |
| Pin EP | EPAD — Exposed pad - must be soldered to ground plane for thermal dissipation |
Typical Applications
LTC2158CUP-14 is suitable for 6 applications: Cellular Base-Station Receivers, Radar and Phased-Array Signal Processing, Test and Measurement Instrumentation, Communications Signal Analyzers, Medical Imaging Systems, Software Defined Radio (SDR).
Cellular Base-Station Receivers
The LTC2158CUP-14's dual simultaneous 310 Msps sampling and 1.25 GHz input bandwidth make it ideal for cellular base-station receiver digitizers. In a typical LTE or 5G NR base-station design, the antenna signal is downconverted to an IF, filtered, and then applied to the ADC's differential inputs. The 88 dB SFDR allows the receiver to detect small signals alongside large blockers, while the 14-bit resolution preserves EVM margins for high-order modulation. The two channels support diversity or multi-band capture from a single converter IC, simplifying PCB layout and reducing BOM cost compared with two single-channel ADCs.
Recommended
Radar and Phased-Array Signal Processing
The LTC2158CUP-14 is well-suited to radar and phased-array receiver front ends where dual simultaneous sampling captures I/Q or two antenna channels on the same clock edge. The 68.8 dB SNR supports detection of small radar returns, and the 1.25 GHz input bandwidth allows direct IF sampling of L-band or S-band radar carriers. Each ADC channel drives an FPGA or ASIC for digital beamforming, with the LVDS output option minimizing digital switching noise. The 64-QFN exposed-pad construction ensures low thermal resistance for continuous full-rate operation in mission-critical systems.
Recommended
Test and Measurement Instrumentation
In high-end oscilloscopes, spectrum analyzers, and arbitrary waveform digitizers, the LTC2158CUP-14's 14-bit resolution and 310 Msps rate deliver the dynamic range and bandwidth needed for accurate signal capture. The 88 dB SFDR keeps harmonic distortion well below the noise floor of typical measurements, and the 1.25 GHz input bandwidth extends usable frequency range into microwave IF regions. Dual channels allow two-probe simultaneous acquisition or trigger/auxiliary digitizing from a single chip. The exposed-pad QFN-64 package provides mechanical robustness and thermal headroom for continuous full-rate operation.
Recommended
Communications Signal Analyzers
The LTC2158CUP-14 supports communications signal analyzers and vector signal analyzer front ends that must capture wide-bandwidth modulated signals with high fidelity. Its 14-bit resolution provides sufficient dynamic range for EVM measurements on 1024-QAM or higher-order constellations, while the 310 Msps rate allows analysis of 100 MHz+ instantaneous bandwidth carriers. The two channels can capture dual-polarized antenna signals or main/auxiliary receiver paths. Differential inputs and integrated common-mode bias simplify the interface to the preceding mixer/IF filter stage.
Recommended
Medical Imaging Systems
Ultrasound and other medical imaging front ends benefit from the LTC2158CUP-14's dual simultaneous 310 Msps channels and 1.25 GHz input bandwidth. Beamformed ultrasound receivers need many coherent ADC channels; the LTC2158CUP-14 captures two channels per chip with tight channel-to-channel phase alignment derived from the shared clock edge. The 14-bit resolution supports the wide dynamic range required for both strong specular reflections and weak tissue echoes. Low-voltage 1.8 V supply operation simplifies integration into portable cart-based ultrasound systems.
Recommended
Software Defined Radio (SDR)
Software-defined radio platforms benefit from the LTC2158CUP-14's wide 1.25 GHz analog input bandwidth, which allows direct sampling of HF, VHF, and lower-UHF signals without an explicit analog downconversion stage. Dual channels support full I/Q capture for quadrature demodulation in DSP, or two independent receiver slices for multi-band listening. The 14-bit resolution preserves dynamic range across both strong broadcast and weak amateur signals. CMOS or DDR LVDS digital outputs interface directly to FPGAs running GNU Radio or vendor DSP frameworks.
Recommended
Recommended Products Summary
Engineering reference data for LTC2158CUP-14 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | LTC2158IUP-14 | LTC2157CUP-14 | LTC2156IUP-14 | LTC2155CUP-12 |
|---|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | 64-QFN (9x9 mm) | 64-QFN (9x9 mm) - same | 64-QFN (9x9 mm) - same | 64-QFN (9x9 mm) - same | 64-QFN (9x9 mm) - same |
| Resolution | 14 bit | 14 bit | 14 bit | 14 bit | 12 bit |
| Sampling Rate | 310 Msps | 310 Msps | 250 Msps | 210 Msps | 250 Msps |
| Number of Channels | 2 simultaneous | 2 simultaneous | 2 simultaneous | 2 simultaneous | 2 simultaneous |
| Output Format | CMOS / DDR LVDS | CMOS / DDR LVDS | CMOS / DDR LVDS | CMOS / DDR LVDS | CMOS / DDR LVDS |
| RoHS Status | Compliant (PBF) | Compliant (PBF) | Compliant (PBF) | Compliant (PBF) | Compliant (PBF) |
Key Differentiators
- Highest sample rate in 64-QFN dual-ADC family (vs LTC2157CUP-14)
- Higher 1.25 GHz input bandwidth for IF sampling (vs LTC2156IUP-14)
- 14-bit resolution vs 12-bit option (vs LTC2155CUP-12)
- Dual simultaneous sampling on a single chip (vs LTC2151CUJ-14 (single-channel 40-QFN))
Design Notes
Each AVDD and OVDD pin must be decoupled individually with a 0.1 uF ceramic capacitor placed within 5 mm of the pin and a 10 uF bulk capacitor placed nearby. Use a low-noise LDO such as the LT3042 or LT1764 upstream of the 1.8 V analog rail to minimize supply-induced jitter. Avoid sharing the ADC analog supply return path with digital logic return currents; use a star-ground topology at the exposed pad.
The exposed pad (EPAD) must be soldered to a continuous ground plane with multiple thermal vias for heat extraction. Route the differential clock (CLK+/CLK-) and analog inputs (AIN1+, AIN1-, AIN2+, AIN2-) as 100 ohm differential striplines with length matching better than 1 mm. Keep digital LVDS output traces short and routed over a continuous ground reference to control common-mode noise.
Source the ADC sampling clock from a low-jitter clock generator such as the AD9516-0 or HMC7044 with RMS jitter below 200 fs to preserve SNR at the full 310 Msps rate. Avoid using FPGA PLLs for the ADC clock because their jitter is typically too high. For LVDS output mode, terminate the differential pairs with 100 ohm near the receiver FPGA inputs to minimize reflections.
Do not omit the reference decoupling caps on REFT and REFB - this directly degrades SFDR. Ensure the input common-mode voltage (VCM) pins are bypassed with 0.1 uF caps; floating these pins causes linearity errors. The SENSE pin must be tied to AGND for internal reference mode or to AVDD for external reference mode per datasheet. Failure to set SENSE correctly will result in incorrect full-scale range.
Compliance Information
#PBF suffix indicates lead-free RoHS-compliant finish per Analog Devices ordering information. Industrial temperature grade variant (LTC2158IUP-14) is also available. AEC-Q100 not applicable - this is a commercial/industrial grade high-speed ADC.
