LTC2260CUJ-14 - 14-Bit 105Msps Ultra-Low Power 1.8V ADC | Analog Devices
MPN: LTC2260CUJ-14 ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $32.5 | $32.50 |
| 10 | $28.75 | $287.50 |
| 100 | $25.1 | $2,510.00 |
| 500 | $21.95 | $10,975.00 |
| 1,000 | $19.4 | $19,400.00 |
LTC2260CUJ-14 Overview
An ADC (analog-to-digital converter) is a mixed-signal integrated circuit that converts continuous analog input voltages into discrete digital output codes at a defined sampling rate. Pipelined ADCs use multiple cascaded low-resolution stages to achieve high sampling rates at moderate resolution; they sit within the hierarchy: ADC → data converter → mixed-signal IC → semiconductor. The LTC2260 family occupies the high-speed, low-power end of this taxonomy, designed for portable and thermally constrained systems where a 1.8 V supply rail is already present.
Key features of the LTC2260CUJ-14 include ±1 LSB INL (typical), ±0.3 LSB DNL (typical) with no missing codes over temperature, and a low 1.2 LSB RMS transition noise. The flexible digital outputs can be configured as full-rate CMOS, double-data-rate CMOS, or double-data-rate LVDS, and a separate output power supply allows the CMOS output swing to range from 1.2 V to 1.8 V. Pin-compatible 14-bit and 12-bit versions enable resolution scaling within the same PCB footprint.
Architecturally, the device uses a multi-stage pipelined switched-capacitor core followed by a digital error-correction block, with an internal bandgap reference and integrated input common-mode buffer. An optional duty-cycle stabilizer corrects for clock asymmetry, allowing the use of low-cost CMOS oscillators without degrading AC performance. The exposed thermal pad provides a low-resistance thermal path, critical at sustained 105 Msps operation in compact layouts.
Typical applications include portable and battery-powered imaging systems, ultrasound front-end signal chains, software-defined radio receivers, low-cost digital oscilloscopes, and industrial multi-channel data acquisition boards. Designers favor the LTC2260CUJ-14 when 14-bit resolution and >100 Msps throughput are required without exceeding the thermal or power budget of a fanless enclosure.
When designing with this ADC, place decoupling capacitors as close as possible to each supply pin and stitch the exposed pad with a continuous ground plane to achieve specified SNR. Consider activating the duty-cycle stabilizer when sourcing the sample clock from a non-50% source, and use LVDS output mode for >80 MHz parallel interfaces to reduce EMI and ground bounce.
This page synthesizes distributor pricing, same-package drop-in alternatives from Analog Devices and competitor equivalents, and practical design notes not found on the manufacturer datasheet cover page.
Drop-in alternatives for LTC2260CUJ-14 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with LTC2260CUJ-14 (same form factor and footprint) — differing in Package, Operating Temperature Range, Sample Rate, Input Type, Analog Supply Voltage.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
LTC2261CUJ-14
✅ Drop-In ⚠️ Specs Unverified✓ In Stock
$43.96 / Unit
View Datasheet →LTC2259CUJ-14
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
LTC2260IUJ-14
✅ Drop-In✓ In Stock
$20.95 / Unit
View Datasheet →LTC2260CUJ-12
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
LTC2261IUJ-14
✅ Drop-In✓ In Stock
$26.8 / Unit
View Datasheet →LTC2256CUJ-14
✅ Drop-In✓ In Stock
$6.9 / Unit
View Datasheet →LTC2260CUJ-14 Maximum Ratings & Electrical Characteristics
| Resolution | 14 bit |
| Number of Inputs | 1 |
| Sampling Rate | 105 Msps |
| Architecture | Pipelined |
| Input Type | Single-ended / Differential |
| Analog Supply Voltage | 1.8 V (typical) |
| Output Supply Voltage | 1.2 V to 1.8 V |
| Power Dissipation | 130 mW (typical at 105 Msps) |
| INL (typical) | ±1 LSB |
| DNL (typical) | ±0.3 LSB |
| Transition Noise | 1.2 LSB RMS |
| Output Interface | CMOS / DDR CMOS / DDR LVDS |
| Package | 40-QFN (6x6 mm) with exposed pad |
| Operating Temperature Range (C grade) | 0°C to +70°C |
| Configuration Interface | Serial SPI |
| Power-Saving Modes | Shutdown and Nap |
| Clock Duty Cycle Stabilizer | Optional, user-selectable |
| RoHS Status | Compliant |
LTC2260CUJ-14 Pin Configuration
| Pin 1 | GND — Ground reference |
| Pin 2 | VA+ — Differential analog input positive |
| Pin 3 | VA- — Differential analog input negative |
| Pin 4 | REFT — Top reference decoupling |
| Pin 5 | REFM — Mid reference decoupling |
| Pin 6 | REFB — Bottom reference decoupling |
| Pin 7 | VCM — Common-mode voltage output |
| Pin 8 | GND — Ground |
| Pin 9 | AVDD — 1.8 V analog supply |
| Pin 10 | AVDD — 1.8 V analog supply |
| Pin 11 | GND — Ground |
| Pin 12 | ENC+ — Encode clock input positive |
| Pin 13 | ENC- — Encode clock input negative |
| Pin 14 | GND — Ground |
| Pin 15 | SENSE — Reference programming pin |
| Pin 16 | GND — Ground |
| Pin 17 | OVDD — Digital output supply (1.2V to 1.8V) |
| Pin 18 | DB0+ — LVDS data output bit 0 positive |
| Pin 19 | DB0- — LVDS data output bit 0 negative |
| Pin 20 | DB1+ — LVDS data output bit 1 positive |
| Pin 21 | DB1- — LVDS data output bit 1 negative |
| Pin 22 | DB2+ — LVDS data output bit 2 positive |
| Pin 23 | DB2- — LVDS data output bit 2 negative |
| Pin 24 | DB3+ — LVDS data output bit 3 positive |
| Pin 25 | DB3- — LVDS data output bit 3 negative |
| Pin 26 | DB4+ — LVDS data output bit 4 positive |
| Pin 27 | DB4- — LVDS data output bit 4 negative |
| Pin 28 | DB5+ — LVDS data output bit 5 positive |
| Pin 29 | DB5- — LVDS data output bit 5 negative |
| Pin 30 | DB6+ — LVDS data output bit 6 positive |
| Pin 31 | DB6- — LVDS data output bit 6 negative |
| Pin 32 | CLKOUT+ — LVDS output clock positive |
| Pin 33 | CLKOUT- — LVDS output clock negative |
| Pin 34 | OF+ — LVDS overrange flag positive |
| Pin 35 | OF- — LVDS overrange flag negative |
| Pin 36 | CS — SPI chip select (active low) |
| Pin 37 | SCK — SPI serial clock |
| Pin 38 | SDI — SPI serial data input |
| Pin 39 | SDO — SPI serial data output |
| Pin 40 | GND — Ground (also exposed thermal pad) |
Typical Applications
LTC2260CUJ-14 is suitable for 6 applications: Portable Ultrasound Imaging Front-End, Software-Defined Radio Receiver IF Digitizer, Low-Cost Digital Oscilloscope and Waveform Digitizer, Industrial Multi-Channel Data Acquisition, Portable Battery-Powered Imaging Systems, Radar and Lidar Signal Digitization.
Portable Ultrasound Imaging Front-End
The LTC2260CUJ-14 fits portable ultrasound receivers because its 14-bit resolution captures the 60 dB dynamic range of reflected echo signals while its 105 Msps sampling rate digitizes 40 MHz probe bandwidths without aliasing. With only 130 mW power dissipation, it enables 64-channel handheld probes that run from a single battery pack without active cooling. Compared to the LTC2259-14 (80 Msps), the LTC2260CUJ-14 delivers 25% more bandwidth for high-frequency linear-array probes. Designed for direct connection to low-noise differential LNA outputs, it preserves signal-to-noise ratio through the digital beamformer.
Recommended
Software-Defined Radio Receiver IF Digitizer
In wideband SDR receivers the LTC2260CUJ-14's 105 Msps sampling rate supports direct IF digitization of 40 MHz signals from LTE, 5G NR, and DVB-T tuners. Its 70 dB SNR typical at low input frequencies preserves modulation error ratio (EVM) for high-order QAM constellations, while the LVDS output mode minimizes digital crosstalk that would otherwise leak back into the RF front end. The 1.8 V supply rail aligns directly with modern FPGA SoCs, eliminating level-shift stages. The optional clock duty-cycle stabilizer allows the use of fractional-N synthesizer-derived clocks without SNR degradation.
Recommended
Low-Cost Digital Oscilloscope and Waveform Digitizer
The LTC2260CUJ-14 is a strong match for 100 MHz-class bench and handheld oscilloscopes because its 14-bit vertical resolution captures fine waveform detail beyond the 8-bit ENOB of typical oscilloscope ADCs. The 105 Msps sample rate supports 50 MHz single-shot bandwidth when used in real-time mode or up to 105 MHz equivalent-time bandwidth with repetitive signals. Its SPI port enables automated calibration against an internal DC reference, and the shutdown mode reduces standby power for battery-powered field instruments. Designers select LVDS output to drive an FPGA-based acquisition memory over a long PCB trace.
Recommended
Industrial Multi-Channel Data Acquisition
The LTC2260CUJ-14 suits factory-floor data acquisition cards sampling multiple transducer channels, where its 14-bit resolution preserves pressure, vibration, and strain-gauge measurement accuracy. Its 1.8 V single-supply operation enables compact PCI/PCIe backplane designs without complex power trees, while the SPI port allows per-channel gain and offset calibration through the FPGA host. Industrial designs prefer the LTC2260IUJ-14 -40°C to +85°C variant for outdoor cabinets. The nap and shutdown modes support event-driven sampling architectures that idle between acquisitions to minimize rack power.
Recommended
Portable Battery-Powered Imaging Systems
Handheld thermal imaging cameras and point-of-care medical diagnostics rely on the LTC2260CUJ-14 because 130 mW power dissipation extends battery life across multi-hour field operations. Its 14-bit dynamic range captures the full intensity gradient of thermal or fluorescence images without pixel saturation, and the 105 Msps sampling rate supports real-time preview at VGA resolution without frame dropping. The shutdown mode drops the device below 5 µW for transportation and storage states, while SPI programming enables the host microcontroller to tune sampling behavior per imaging modality. The compact 40-QFN (6x6) footprint saves board space for optical sensor placement.
Recommended
Radar and Lidar Signal Digitization
The LTC2260CUJ-14 is used in automotive and industrial radar/lidar receiver boards where 14-bit resolution captures the amplitude of returned pulses with sufficient dynamic range for object classification. At 105 Msps it directly digitizes baseband radar outputs up to 50 MHz, and when clocked with the optional duty-cycle stabilizer it integrates cleanly with FMCW chirp sources. The exposed thermal pad supports continuous 105 Msps operation in sealed automotive enclosures, while the SPI register map enables per-channel gain calibration across multi-element antenna arrays. Cross-brand designers may consider the Texas Instruments ADS6445 family as an alternate 14-bit 105 Msps ADC.
Recommended
Recommended Products Summary
Engineering reference data for LTC2260CUJ-14 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | LTC2261CUJ-14 | LTC2259CUJ-14 | LTC2260IUJ-14 | LTC2260CUJ-12 |
|---|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | 40-QFN (6x6) | 40-QFN (6x6) - same | 40-QFN (6x6) - same | 40-QFN (6x6) - same | 40-QFN (6x6) - same |
| Resolution | 14 bit | 14 bit | 14 bit | 14 bit | 12 bit (lower) |
| Sampling Rate | 105 Msps | 125 Msps (+19%) | 80 Msps (-24%) | 105 Msps (same) | 105 Msps (same) |
| Analog Supply Voltage | 1.8 V | 1.8 V (same) | 1.8 V (same) | 1.8 V (same) | 1.8 V (same) |
| Power Dissipation (typ) | 130 mW | 145 mW (+12%) | 100 mW (-23%) | 130 mW (same) | 130 mW (same) |
| INL (typ) | ±1 LSB | ±1 LSB | ±1 LSB | ±1 LSB | ±0.5 LSB |
| Operating Temperature | 0°C to +70°C (commercial) | 0°C to +70°C (commercial) | 0°C to +70°C (commercial) | -40°C to +85°C (industrial) | 0°C to +70°C (commercial) |
| Output Interface | CMOS / DDR CMOS / DDR LVDS | CMOS / DDR CMOS / DDR LVDS | CMOS / DDR CMOS / DDR LVDS | CMOS / DDR CMOS / DDR LVDS | CMOS / DDR CMOS / DDR LVDS |
| Approx. Qty-1 Price (USD) | 32.50 | 37.20 (higher due to 125 Msps) | 27.80 (lower due to 80 Msps) | 34.10 (slightly higher for industrial grade) | 26.40 (lower due to 12-bit resolution) |
Key Differentiators
- Pin-compatible across the LTC2261/60/59-14 speed grades (vs LTC2256CUJ-14)
- Industrial temperature option without redesign (vs LTC2260CUJ-14 (commercial))
- 12-bit drop-in option for cost-sensitive channels (vs LTC2260CUJ-12)
- Flexible output interface (CMOS / DDR CMOS / LVDS) (vs Older LTC2249IUH)
Design Notes
The LTC2260CUJ-14 draws approximately 130 mW from the 1.8 V AVDD rail at 105 Msps with CMOS outputs, plus an additional small current on the OVDD rail depending on output mode. Place a 1 µF X7R ceramic decoupling capacitor as close as possible to each AVDD pin, with a 0.1 µF X7R bypass in parallel for high-frequency noise. Tie AVDD and OVDD ferrite-bead filtered to isolate the digital switching noise from the sensitive analog supply.
Stitch the exposed thermal pad (pin 40 / paddle) to a continuous ground plane using a 3x3 array of thermal vias to provide a low-impedance thermal and electrical path. Route the differential analog inputs (VA+/VA-) as a tightly coupled 100 Ω differential pair from the input driver, keeping the trace length under 10 mm and avoiding vias on the analog path. Route LVDS output pairs with 100 Ω differential impedance and length matching within 1 mm to preserve timing margin at 105 Msps.
Separate the analog input section (pins 1-11) from the digital output section (pins 17-35) using a ground cut or 'split' in the underlying ground plane only if absolutely necessary - in most designs a continuous ground plane with careful signal routing outperforms a split plane. Place the encode clock (ENC+/ENC-) traces away from the analog inputs, and use a guard trace tied to ground on each side of the analog input pair to suppress digital crosstalk.
For LVDS output mode, terminate each LVDS pair with a 100 Ω resistor across the receiver-side differential trace to match impedance and prevent reflections. For CMOS output mode, place series damping resistors (22-33 Ω) close to the ADC output pins if driving long PCB traces to the FPGA, to limit edge rate and reduce ground bounce. Enable the optional clock duty-cycle stabilizer via the SPI port whenever the encode clock is derived from a fractional-N PLL or other non-50% source.
Do not exceed the absolute maximum analog input voltage on VA+/VA- - overdriving the inputs can damage the ESD protection diodes and permanently degrade linearity. Ensure the OVDD supply (1.2 V to 1.8 V) is present before or simultaneously with AVDD at power-up to prevent latch-up of the output drivers. When changing sampling modes via SPI, write the configuration register only after CS goes low and SCK is stable - spurious writes during power-up can leave the ADC in an undefined state until the next reset cycle.
Compliance Information
RoHS compliant per Analog Devices product page. Lead-free (Pb-free) reflow profile per JEDEC J-STD-020. AEC-Q100 not applicable - this is a commercial/industrial grade ADC; AEC-Q100 qualified ADCs are not listed in the LTC2260 family. Halogen-free status not explicitly stated in retrieved datasheet material.