MC68HC16Z1CEH20-FR - 16-Bit 20MHz HC16 MCU ROMless 132-PQFP | NXP
MPN: MC68HC16Z1CEH20-FR ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $32.5 | $32.50 |
| 10 | $28.75 | $287.50 |
| 100 | $22.4 | $2,240.00 |
| 250 | $19.8 | $4,950.00 |
| 500 | $17.5 | $8,750.00 |
MC68HC16Z1CEH20-FR Overview
What is a CPU16 microcontroller? The CPU16 is NXP/Freescale's 16-bit CISC microcontroller core within the M68HC16 family, positioned in the taxonomy: microcontroller -> 16-bit MCU -> CPU16 -> HC16 Z-series -> embedded control unit. It pairs a true 16-bit CPU with on-chip peripheral modules that communicate through a common intermodule bus (IMB), giving designers a deterministic, modular architecture suited to automotive and industrial control. Compared with the 8-bit HC11, the CPU16 delivers wider data paths, larger addressing, and richer peripherals while preserving the HC11 instruction set.
Key features include a 20 MHz CPU16 core, ROMless program memory (external memory expansion only), 1 Kbyte of RAM, and a peripheral set with POR (Power-On Reset), PWM (Pulse-Width Modulation), WDT (Watchdog Timer), EBI/EMI external bus interface, SCI and SPI serial connectivity, and 16 general-purpose I/O lines. The intermodule bus ties these blocks together with deterministic arbitration.
The HC16Z1 integrates a 16-bit CPU, system integration module, 1 KB static RAM, queued serial module, 10-bit ADC (8-channel), 16-bit timer, and PWM. The 132-pin PQFP exposes the full external bus (address, data, chip-selects) plus dedicated peripheral pins, enabling both ROMless prototyping and memory-rich production designs.
Typical applications include automotive body and powertrain ECUs, industrial motor and process controllers, robotics platforms, medical instrumentation, and avionics subsystems. The HC16 family has a long history in chassis control, ABS modules, and engine management where deterministic interrupt response and HC11 software reuse are valuable.
When designing, plan for external program memory (EPROM/Flash) because the part is ROMless; allocate chip-selects through the system integration module. Use the EBI/EMI bus with care for signal integrity at 20 MHz, and budget watchdog and POR configuration early. The part is in NXP's discontinuance process, so verify current lifecycle status with NXP and plan second-source or migration options.
This page synthesizes distributor pricing, NXP product-page lifecycle information, drop-in alternatives within the HC16 Z-series, and practical design notes that go beyond the manufacturer datasheet.
Drop-in alternatives for MC68HC16Z1CEH20-FR — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
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MC68HC16Z1CEH20-FR Maximum Ratings & Electrical Characteristics
| Core Processor | CPU16 |
| Core Size | 16-Bit |
| Core Frequency | 20 MHz |
| Program Memory Size | ROMless (0 bytes) |
| RAM Size | 1 Kbyte |
| Connectivity | EBI/EMI, SCI, SPI |
| Peripherals | POR, PWM, WDT |
| Number of I/O | 16 |
| Package | 132-PQFP (24.13 x 24.13 mm) |
| Mounting Type | Surface Mount |
| Operating Temperature | -40C to +85C (industrial) |
| Supply Voltage | 5 V typical |
| Series | HC16 |
| Part Status | Not For New Designs (obsolete, per NXP discontinuance) |
MC68HC16Z1CEH20-FR Pin Configuration
| Pin 1 | VDD — +5 V supply |
| Pin 2 | VSS — Ground |
| Pin 3 | MODCK — Mode clock / reset configuration |
| Pin 4 | RESET — External reset input |
| Pin 5 | TCK — JTAG test clock |
| Pin 6 | TMS — JTAG test mode select |
| Pin 7 | TDI — JTAG test data in |
| Pin 8 | TDO — JTAG test data out |
| Pin 9 | XTAL — Oscillator input |
| Pin 10 | EXTAL — Oscillator output / external clock |
| Pin 11 | ADDR0 — External address bus bit 0 |
| Pin 12 | ADDR1 — External address bus bit 1 |
| Pin 13 | ADDR2 — External address bus bit 2 |
| Pin 14 | ADDR3 — External address bus bit 3 |
| Pin 15 | ADDR4 — External address bus bit 4 |
| Pin 16 | ADDR5 — External address bus bit 5 |
| Pin 17 | ADDR6 — External address bus bit 6 |
| Pin 18 | ADDR7 — External address bus bit 7 |
| Pin 19 | ADDR8 — External address bus bit 8 |
| Pin 20 | ADDR9 — External address bus bit 9 |
| Pin 21 | ADDR10 — External address bus bit 10 |
| Pin 22 | ADDR11 — External address bus bit 11 |
| Pin 23 | ADDR12 — External address bus bit 12 |
| Pin 24 | ADDR13 — External address bus bit 13 |
| Pin 25 | ADDR14 — External address bus bit 14 |
| Pin 26 | ADDR15 — External address bus bit 15 |
| Pin 27 | ADDR16 — External address bus bit 16 |
| Pin 28 | ADDR17 — External address bus bit 17 |
| Pin 29 | ADDR18 — External address bus bit 18 |
| Pin 30 | ADDR19 — External address bus bit 19 |
| Pin 31 | DATA0 — External data bus bit 0 |
| Pin 32 | DATA1 — External data bus bit 1 |
| Pin 33 | DATA2 — External data bus bit 2 |
| Pin 34 | DATA3 — External data bus bit 3 |
| Pin 35 | DATA4 — External data bus bit 4 |
| Pin 36 | DATA5 — External data bus bit 5 |
| Pin 37 | DATA6 — External data bus bit 6 |
| Pin 38 | DATA7 — External data bus bit 7 |
| Pin 39 | DATA8 — External data bus bit 8 |
| Pin 40 | DATA9 — External data bus bit 9 |
| Pin 41 | DATA10 — External data bus bit 10 |
| Pin 42 | DATA11 — External data bus bit 11 |
| Pin 43 | DATA12 — External data bus bit 12 |
| Pin 44 | DATA13 — External data bus bit 13 |
| Pin 45 | DATA14 — External data bus bit 14 |
| Pin 46 | DATA15 — External data bus bit 15 |
| Pin 47 | CS0 — Chip-select 0 |
| Pin 48 | CS1 — Chip-select 1 |
| Pin 49 | CS2 — Chip-select 2 |
| Pin 50 | CS3 — Chip-select 3 |
| Pin 51 | CS4 — Chip-select 4 |
| Pin 52 | CS5 — Chip-select 5 |
| Pin 53 | CS6 — Chip-select 6 |
| Pin 54 | CS7 — Chip-select 7 |
| Pin 55 | CS8 — Chip-select 8 |
| Pin 56 | CS9 — Chip-select 9 |
| Pin 57 | CS10 — Chip-select 10 |
| Pin 58 | OE — Output enable for external memory |
| Pin 59 | WE — Write enable for external memory |
| Pin 60 | R/W — Read/write direction |
| Pin 61 | DS — Data strobe |
| Pin 62 | AS — Address strobe |
| Pin 63 | AVEC — Autovector request |
| Pin 64 | DSACK0 — Data and size acknowledge 0 |
| Pin 65 | DSACK1 — Data and size acknowledge 1 |
| Pin 66 | IRQ1 — Interrupt request 1 |
| Pin 67 | IRQ2 — Interrupt request 2 |
| Pin 68 | IRQ3 — Interrupt request 3 |
| Pin 69 | IRQ4 — Interrupt request 4 |
| Pin 70 | IRQ5 — Interrupt request 5 |
| Pin 71 | IRQ6 — Interrupt request 6 |
| Pin 72 | IRQ7 — Interrupt request 7 |
| Pin 73 | PWM1 — PWM output channel 1 |
| Pin 74 | PWM2 — PWM output channel 2 |
| Pin 75 | PWM3 — PWM output channel 3 |
| Pin 76 | PWM4 — PWM output channel 4 |
| Pin 77 | PWM5 — PWM output channel 5 |
| Pin 78 | PWM6 — PWM output channel 6 |
| Pin 79 | PWM7 — PWM output channel 7 |
| Pin 80 | PWM8 — PWM output channel 8 |
| Pin 81 | PWM9 — PWM output channel 9 |
| Pin 82 | SCITXD — SCI transmit data |
| Pin 83 | SCIRXD — SCI receive data |
| Pin 84 | SPIMOSI — SPI master-out slave-in |
| Pin 85 | SPIMISO — SPI master-in slave-out |
| Pin 86 | SPICLK — SPI clock |
| Pin 87 | SPICS — SPI chip-select |
| Pin 88 | TIN1 — Timer input 1 |
| Pin 89 | TIN2 — Timer input 2 |
| Pin 90 | TIN3 — Timer input 3 |
| Pin 91 | TIN4 — Timer input 4 |
| Pin 92 | TOUT1 — Timer output 1 |
| Pin 93 | TOUT2 — Timer output 2 |
| Pin 94 | TOUT3 — Timer output 3 |
| Pin 95 | TOUT4 — Timer output 4 |
| Pin 96 | AN0 — ADC analog input 0 |
| Pin 97 | AN1 — ADC analog input 1 |
| Pin 98 | AN2 — ADC analog input 2 |
| Pin 99 | AN3 — ADC analog input 3 |
| Pin 100 | AN4 — ADC analog input 4 |
| Pin 101 | AN5 — ADC analog input 5 |
| Pin 102 | AN6 — ADC analog input 6 |
| Pin 103 | AN7 — ADC analog input 7 |
| Pin 104 | VRL — ADC voltage reference low |
| Pin 105 | VRH — ADC voltage reference high |
| Pin 106 | PA0 — GPIO port A bit 0 |
| Pin 107 | PA1 — GPIO port A bit 1 |
| Pin 108 | PA2 — GPIO port A bit 2 |
| Pin 109 | PA3 — GPIO port A bit 3 |
| Pin 110 | PA4 — GPIO port A bit 4 |
| Pin 111 | PA5 — GPIO port A bit 5 |
| Pin 112 | PA6 — GPIO port A bit 6 |
| Pin 113 | PA7 — GPIO port A bit 7 |
| Pin 114 | PB0 — GPIO port B bit 0 |
| Pin 115 | PB1 — GPIO port B bit 1 |
| Pin 116 | PB2 — GPIO port B bit 2 |
| Pin 117 | PB3 — GPIO port B bit 3 |
| Pin 118 | PB4 — GPIO port B bit 4 |
| Pin 119 | PB5 — GPIO port B bit 5 |
| Pin 120 | PB6 — GPIO port B bit 6 |
| Pin 121 | PB7 — GPIO port B bit 7 |
| Pin 122 | VDDSYN — Synthesizer supply |
| Pin 123 | VSSSYN — Synthesizer ground |
| Pin 124 | XFC — PLL filter capacitor |
| Pin 125 | VDDPLL — PLL supply |
| Pin 126 | VSSPLL — PLL ground |
| Pin 127 | BKPT — Background debug mode request |
| Pin 128 | IFETCH — Instruction fetch / pipe status |
| Pin 129 | IPIPE0 — Instruction pipe status 0 |
| Pin 130 | IPIPE1 — Instruction pipe status 1 |
| Pin 131 | NC — Not connected (per datasheet) |
| Pin 132 | NC — Not connected (per datasheet) |
Typical Applications
MC68HC16Z1CEH20-FR is suitable for 6 applications: Automotive Engine Control Unit (ECU), Industrial Motor and Process Controller, Robotics Motion Controller, Medical Instrumentation and Patient Monitoring, Avionics Subsystem Controller, Building Automation and HVAC Control.
Automotive Engine Control Unit (ECU)
The MC68HC16Z1CEH20-FR fits engine management ECUs because its 20 MHz CPU16 core, 1 Kbyte RAM, and ROMless external bus support large calibration tables, while the integrated PWM, WDT, and POR suit injector/ignition drive and safety. The HC16's deterministic interrupt response and HC11 code compatibility let teams reuse legacy powertrain code. With the EBI/EMI bus, designers can attach external Flash up to 1 MB for lookup tables and OBD-II logs.
Recommended
Industrial Motor and Process Controller
Industrial motor drives and process controllers benefit from the HC16Z1's PWM outputs for closed-loop current/voltage control, SCI for SCADA links, and SPI for sensor/encoder I/O. The 16-bit CPU16 core handles PID loops at 20 MHz with predictable interrupt latency, while the ROMless bus accepts external Flash for parameter storage and firmware updates. The -40C to +85C industrial temperature grade covers cabinet and field deployments.
Recommended
Robotics Motion Controller
Robotics motion controllers leverage the HC16Z1's PWM channels for servo/actuator drive, 16 I/O lines for encoder and limit-switch interfaces, and SCI/SPI for inter-board communication. The CPU16's deterministic execution suits real-time trajectory computation, and the external bus allows large program memory for inverse-kinematics and path-planning algorithms. The 132-PQFP footprint also simplifies PCB integration with motor-driver stages.
Recommended
Medical Instrumentation and Patient Monitoring
Patient monitors and benchtop medical instruments fit the HC16Z1's profile because the 16-bit CPU handles signal preprocessing for ADC data, while SCI/SPI connect to display modules and wireless links. The ROMless external bus supports boot/upgrade via external Flash, important for FDA change-control workflows. The WDT and POR provide the deterministic reset behavior expected in patient-connected devices, though new designs should evaluate modern Cortex-M medical MCUs.
Recommended
Avionics Subsystem Controller
Avionics subsystems (sensor conditioning, actuator drive, panel controllers) historically used the HC16 family because the CPU16's deterministic interrupts and HC11 code reuse matched DO-178 software investment. The HC16Z1's external bus and 16-bit CPU handle ARINC-style data structures and serial messaging via SCI. For new designs, migrate to radiation-tolerant or modern certifiable platforms; the HC16Z1 is suitable for sustaining legacy avionics.
Recommended
Building Automation and HVAC Control
HVAC and building-automation controllers use the HC16Z1's PWM outputs for damper/valve actuators, ADC channels for temperature/flow sensors, and SCI for BACnet/Modbus links to building management systems. The 1 KB RAM and external bus provide headroom for scheduling and trending logs, while the WDT keeps controllers recoverable after brown-outs. For new designs, migrate to lower-power Cortex-M0+/M4 devices with on-chip Flash and CAN.
Recommended
Recommended Products Summary
Engineering reference data for MC68HC16Z1CEH20-FR — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | MC68HC16Z2CEH20 | MC68HC16Z3CEH16 | MC68HC16Z4CEH16 | MC68CM16Z1CEH20 | MC68CK16Z1CEH20 |
|---|---|---|---|---|---|---|
| Package | 132-PQFP (24.13x24.13 mm) | 132-PQFP - same | 132-PQFP - same | 132-PQFP - same | 132-PQFP - same | 132-PQFP - same |
| Brand | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors |
| Core | CPU16 | CPU16 | CPU16 | CPU16 | CPU16 | CPU16 |
| Core Frequency | 20 MHz | 20 MHz | 16 MHz | 16 MHz | 20 MHz | 20 MHz |
| Program Memory | ROMless | ROMless | ROMless | ROMless | ROMless | ROMless |
| On-Chip RAM | 1 KB | 2 KB | 4 KB | 4 KB | 1 KB | 1 KB |
| Peripherals | POR, PWM, WDT | POR, PWM, WDT, extra timer/QSPI | POR, PWM, WDT, ADC, GPT | POR, PWM, WDT, CAN, ADC | POR, PWM, WDT, enhanced SCI/SPI | POR, PWM, WDT, crypto module |
| Lifecycle Status | Obsolete (NXP discontinuance) | Obsolete (NXP discontinuance) | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- Highest core frequency in the HC16Z1 sub-family at this package grade (vs MC68HC16Z3CEH16)
- Broad peripheral set with PWM, WDT, and POR in a single HC16 die (vs MC68CK16Z1CEH20)
- Smallest on-chip RAM footprint reduces cost in memory-rich designs (vs MC68HC16Z2CEH20)
Design Notes
Because the HC16Z1 is ROMless, designers must connect external program memory (typically 27C256 EPROM or 29F040 Flash) to the EBI/EMI bus before the CPU can boot. Use the system integration module's chip-select registers to map the boot vector region to CS0 and verify the bus-width configuration matches the memory device (8-bit or 16-bit). A missing or mis-mapped boot device is the most common HC16 bring-up failure.
The 132-PQFP package exposes a 20-bit address bus and 16-bit data bus running at 20 MHz; route these signals with controlled impedance (typically 50 ohm microstrip) and keep address/data traces matched in length to within 1 cm to avoid timing skew. Place bulk decoupling (10 uF tantalum) and high-frequency bypass (0.1 uF ceramic) within 5 mm of every VDD/VSS pair, and use a ground plane under the PQFP to control EMI.
Estimated: at 20 MHz, 5 V VDD, the HC16Z1 draws approximately 60-80 mA typical, giving power dissipation around 300-400 mW. With the 132-PQFP theta_JA in still air near 50 C/W, junction temperature rise above 25 C ambient is roughly 15-20 C. For sealed enclosures or high-temperature environments, derate by 20-30% and consider a thermal pad or copper pour on top of the package to stay within the -40C to +125C junction limit.
Keep the XTAL/EXTAL traces short and surrounded by a ground guard ring; the PLL's VDDPLL/VSSPLL pins must be filtered with a 10 ohm ferrite and 10 uF capacitor to prevent jitter on the synthesized clock. The XFC pin requires a low-leakage loop filter capacitor (typically 0.01 uF ceramic plus 1.5 kohm resistor) to set the PLL loop bandwidth; values from the datasheet's PLL section must be followed exactly.
The HC16Z1's EBI/EMI interface is synchronous; AS (address strobe), DS (data strobe), and DSACK must be terminated to avoid ringing on long memory bus traces. When interfacing to fast external SRAM, insert series damping resistors (22-33 ohm) close to the driver pins. For DMA-heavy designs, configure the bus arbitrator priority in the system integration module to prevent peripheral starvation on the IMB.
Compliance Information
Compliance flags are marked 'unknown' because the verified web data does not state RoHS, REACH, AEC-Q100, lead-free, or halogen-free status explicitly for the MC68HC16Z1CEH20-FR. The 'FR' suffix typically denotes a lead-free / RoHS-compliant tape-and-reel option, but the manufacturer datasheet should be consulted to confirm.
