MPC8379EVRANG - 800MHz PowerPC e300c4s MPU | NXP
MPN: MPC8379EVRANG ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $85.5 | $85.50 |
| 10 | $78.2 | $782.00 |
| 100 | $71.4 | $7,140.00 |
| 500 | $64.8 | $32,400.00 |
| 1,000 | $58.3 | $58,300.00 |
MPC8379EVRANG Overview
A microprocessor (MPU) is the central processing unit of an embedded design, executing operating systems, network stacks, and protocol handling code. The MPC83xx PowerQUICC II Pro family sits between simpler microcontrollers and high-end application processors, historically used in routers, switches, DSLAMs, and SOHO networking equipment. Within the NXP portfolio, the MPC83xx hierarchy is: e300 core -> PowerQUICC II Pro -> communications processor -> MPU. This taxonomy matters for engineers sourcing replacements or planning firmware reuse.
Key features include a single e300c4s core with 32KB L1 instruction cache and 32KB L1 data cache, dual integrated 10/100/1000 Ethernet MACs, DDR1/DDR2 memory controller supporting up to 1 GB addressable memory, four DMA channels, and a security engine with hardware-accelerated encryption. The integrated encryption block supports AES, DES/3DES, SHA-1/MD5, and public-key algorithms, eliminating the need for an external crypto coprocessor in VPN, IPsec, and SSL/TLS gateway designs.
The architecture combines the e300c4s superscalar core (derived from Power Architecture technology) with the QUICC Engine communication subsystem, delivering high throughput for packet processing. The device operates from 1.0V core / 1.8V/2.5V/3.3V I/O supplies, manufactured in a 0.09-micron process. The 689-TEPBGA II package exposes a large die for thermal dissipation, suitable for industrial temperature grades.
Typical applications span wired networking routers, secure VPN gateways, industrial PLC controllers, and embedded communication appliances. The integrated Ethernet MACs and encryption engine make it well-matched to IPsec/SSL gateway products where BOM cost and PCB area must be minimized.
Design consideration: routing a 689-ball BGA at 31x31mm requires multilayer PCB stack-up (typically 6-8 layers) with laser-drilled or micro-vias under the package; signal integrity work for DDR2 traces and Gigabit Ethernet MII/RGMII signals is non-trivial and should be validated against the NXP hardware design checklist before layout commitment.
This page consolidates distributor pricing, lifecycle notes, comparison data, and engineering design guidance beyond what is captured in the manufacturer datasheet, to help engineers source and design with the MPC8379EVRANG efficiently.
Drop-in alternatives for MPC8379EVRANG — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with MPC8379EVRANG (same form factor and footprint).
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
MPC8378EVRANG
✅ Drop-In📋 Reference alternative (not in catalog)
MPC8377EVRANG
✅ Drop-In✓ In Stock
$60.4 / Unit
View Datasheet →MPC8379CVRAFG
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
MPC8379ECVRANG
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
MPC8378VVRAFG
✅ Drop-In📋 Reference alternative (not in catalog)
MPC8379EVRANG Maximum Ratings & Electrical Characteristics
| Manufacturer | NXP Semiconductors |
| Series | MPC83xx |
| Core Processor | PowerPC e300c4s |
| Number of Cores | 1 |
| Core Architecture | 32-Bit Power Architecture |
| Core Frequency | 800 MHz |
| Co-Processor / DSP | QUICC Engine |
| L1 Cache (I/D) | 32 KB / 32 KB |
| Operating Voltage | 1.0 V core / 1.8 V / 2.5 V / 3.3 V I/O |
| Process Technology | 0.09 um CMOS |
| Package | 689-TEPBGA II (31x31 mm) with exposed pad |
| Mounting Type | Surface Mount |
| Connectivity | I2C, PCI, SPI, UART, USB |
| Ethernet MACs | 2x 10/100/1000 Mbps |
| Security Features | AES, DES/3DES, SHA-1/MD5, PK acceleration |
| DMA Channels | 4 |
| RoHS Status | Compliant |
| Lead-Free | Yes |
MPC8379EVRANG 689-tepbga ii (31x31 mm) with exposed pad Pin Configuration Guide
Pin configuration for MPC8379EVRANG (689-tepbga ii (31x31 mm) with exposed pad package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for MPC8379EVRANG.
Refer to the datasheet for full pin configuration.
Typical Applications
MPC8379EVRANG is suitable for 6 applications: Enterprise Wired Router, IPsec/SSL VPN Gateway, Industrial Control and PLC Gateway, Network Attached Storage Controller, DSLAM / Broadband Access Node, Secure Access Point Controller.
Enterprise Wired Router
The MPC8379EVRANG is well-suited for enterprise wired routers and branch-office gateways due to its 800 MHz PowerPC e300c4s core, dual integrated Gigabit Ethernet MACs, and QUICC Engine communications subsystem. The hardware encryption engine accelerates IPsec and SSL/TLS tunnel termination at line rate, eliminating the need for an external crypto ASIC. Placed at the heart of the routing engine, the part handles forwarding table lookup, ACL processing, and packet classification while keeping CPU headroom for management-plane tasks. The DDR1/DDR2 controller supports up to 1 GB of addressable memory for routing tables and connection state.
Recommended
IPsec/SSL VPN Gateway
The integrated AES, DES/3DES, SHA-1, MD5, and public-key acceleration engine makes the MPC8379EVRANG ideal for IPsec and SSL VPN gateway designs where hardware offload of cryptography is essential to maintain wire-speed throughput. By terminating tunnels in hardware, the e300c4s core is freed for IKE negotiation, NAT traversal, and policy management. Compared with software-only crypto on a generic MPU, this approach typically yields 3-5x throughput improvement at equivalent clock rate, reducing bill-of-materials cost and PCB area.
Recommended
Industrial Control and PLC Gateway
Industrial PLC gateways and protocol-conversion appliances benefit from the MPC8379EVRANG's combination of deterministic PowerPC core, dual Gigabit Ethernet, and rich peripheral mix (PCI, USB, I2C, SPI, UART). The device can run a real-time OS such as VxWorks or Linux with PREEMPT_RT for deterministic packet delivery on industrial Ethernet networks. Its 689-TEPBGA II package and 0.09 um process support industrial temperature grades, and the integrated QUICC Engine handles time-sensitive protocol acceleration for Profinet, EtherNet/IP, or Modbus TCP gateways.
Recommended
Network Attached Storage Controller
The MPC8379EVRANG serves well as a small/medium-business NAS controller, combining SATA/PCI peripheral connectivity via the PCI bus with a fast DDR2 memory controller that sustains streaming throughput. The QUICC Engine handles TCP/IP offload, reducing CPU load during multi-client file transfers. The 800 MHz e300c4s core is sufficient for RAID parity computation at gigabit wire speed for typical home/SMB workloads. Its hardware crypto engine supports SMB3 encryption and Kerberos authentication acceleration.
Recommended
DSLAM / Broadband Access Node
The MPC8379EVRANG fits into DSLAM line-card controllers and broadband access nodes where multiple DSL channels must be aggregated and forwarded upstream. The QUICC Engine's multi-channel HDLC and ATM support, combined with the PCI bus for DSL PHY interfacing, allows a single part to handle many subscriber lines. The hardware encryption engine supports secure PPPoE, L2TP, and IPsec termination per session, while the DDR2 controller buffers large amounts of downstream traffic during peak hours.
Recommended
Secure Access Point Controller
Enterprise secure access points that need WPA2-Enterprise authentication and on-device VPN tunnel support leverage the MPC8379EVRANG's hardware AES/SHA-1 acceleration and dual Gigabit MACs for upstream and downstream traffic. The e300c4s core runs the access-point control-plane firmware while QUICC Engine handles wireless-frame encapsulation. Compared to running crypto on a generic ARM Cortex-A class MPU, the integrated engine sustains higher concurrent-client counts at lower power.
Recommended
Recommended Products Summary
Engineering reference data for MPC8379EVRANG — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | MPC8378EVRANG | MPC8377EVRANG | MPC8379CVRAFG | MPC8379ECVRANG | MPC8378VVRAFG |
|---|---|---|---|---|---|---|
| Brand | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors |
| Package | 689-TEPBGA II (31x31) | 689-TEPBGA II - same | 689-TEPBGA II - same | 689-TEPBGA II - same | 689-TEPBGA II - same | 689-TEPBGA II - same |
| Core Frequency | 800 MHz | 800 MHz | 667 MHz | 800 MHz | 800 MHz | 667 MHz |
| Hardware Encryption | Yes (AES/DES/SHA/PK) | No | No | Yes (AES/DES/SHA/PK) | Yes (AES/DES/SHA/PK) | No |
| Gigabit Ethernet MACs | 2 | 2 | 2 | 2 | 2 | 2 |
| Memory Controller | DDR1/DDR2 | DDR1/DDR2 | DDR1/DDR2 | DDR1/DDR2 | DDR1/DDR2 | DDR1/DDR2 |
| QUICC Engine | Yes | Yes | Yes | Yes | Yes | Yes |
| Temperature Grade | Extended (industrial) | Extended | Extended | Industrial | Extended | Industrial |
| Param Match | 100% | 90% | 80% | 100% | 100% | 90% |
Key Differentiators
- Integrated hardware encryption accelerator (vs MPC8378EVRANG)
- 800 MHz top bin in MPC837x series (vs MPC8377EVRANG)
- Dual Gigabit Ethernet MACs integrated (vs External MAC companion chip)
- QUICC Engine multi-protocol acceleration (vs Software-only HDLC/ATM handling)
Design Notes
The 689-ball TEPBGA II package at 31x31mm requires a 6-8 layer PCB stack-up with micro-vias under the package. Use a 1 oz copper pour on inner layers stitched with 8G thermal vias on the exposed pad to maintain junction temperature within spec at 800 MHz. Per NXP hardware checklist, keep all DDR2 traces length-matched within 25 mil and route Gigabit Ethernet MII/RGMII signals over a continuous reference plane. Decoupling: place 0.1 uF X7R ceramics at every power pin pair plus bulk 10 uF tantalums near the package perimeter.
Estimated: at 800 MHz with 1.0 V supply drawing around 1.5 A core current plus I/O, total power dissipation is approximately 2-3 W. The exposed thermal pad must be soldered to a copper pour of at least 1 sq inch with thermal vias; without it junction temperature can exceed 105 C and trigger thermal protection. For sealed enclosures, derate clock frequency or add airflow. Use the NXP thermal model document to compute theta-JA in your specific board stack-up.
Do not assume the security engine (E suffix) is enabled by default - the boot configuration words in RCW (Reset Configuration Word) must explicitly enable the SEC block. Common mistakes include incorrect DDR2 ZQ calibration, missing 100-ohm differential terminations on PCI bus, and confusing the e300c4s with the e500v2 (used in QorIQ) when porting firmware. Verify the silicon revision against the NXP errata document before mass production.
Route DDR2 data/clock/address groups on inner stripline with reference to a solid ground plane 5 mils below. Target 50-ohm single-ended impedance for SDRAM signals, 100-ohm differential for clocks. Keep trace length mismatches under 25 mil within a byte lane. Gigabit Ethernet MII/RGMII traces must be length-matched within 50 mil and routed over an unbroken ground plane; avoid crossing split power regions.
Compliance Information
RoHS and REACH compliance per NXP product declaration. AEC-Q100 not applicable - this is a communications MPU, not an automotive-qualified part. For automotive designs NXP offers different part numbers.
