MPC855TZQ66D4 - 66MHz PowerQUICC MPU, 357-PBGA | NXP
MPN: MPC855TZQ66D4 ⚠ Last Time Buy| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $95 | $95.00 |
| 10 | $88 | $880.00 |
| 100 | $78 | $7,800.00 |
| 500 | $72 | $36,000.00 |
| 1,000 | $67 | $67,000.00 |
MPC855TZQ66D4 Overview
A PowerQUICC processor is a System-on-Chip (SoC) that integrates a general-purpose embedded CPU with a dedicated communications processor. The MPC855T belongs to the broader MPC860 PowerQUICC family, which historically served as the workhorse of SOHO routers, ISDN/DSL access multiplexers, Voice-over-IP gateways, and industrial control planes. Architecturally, PowerQUICC sits within the Power Architecture embedded SoC hierarchy, and the MPC8xx core itself is a single-issue, hardware-multiplied PowerPC core distinct from later PowerQUICC II/III (MPC82xx/MPC83xx/MPC85xx) devices.
Key features include a 66 MHz core clock, 32-bit data path, integrated 10/100 Mbit/s Fast Ethernet controller, dedicated CPM for protocol offload, on-chip memory management, programmable interrupt controller, and a parallel bus interface. Industrial temperature grade (0C to +95C) and a long-lifecycle product status make this device suitable for legacy telecom and industrial control platforms where re-qualification cost dominates.
Typical applications include SOHO routers, xDSL modems, Ethernet bridges, industrial serial-to-Ethernet gateways, and access multiplexer line cards. When designing with this device, verify the supply voltage (3.3 V core, 3.3 V I/O), the JTAG chain layout, and the PBGA thermal management using a four-layer minimum PCB with continuous ground/power planes.
Drop-in alternatives for MPC855TZQ66D4 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with MPC855TZQ66D4 (same form factor and footprint) — differing in Manufacturer, Mounting Type, Package, Series.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
MPC860PCZQ66D4
✅ Drop-In📋 Reference alternative (not in catalog)
MPC860ENCZQ66D4
✅ Drop-In📋 Reference alternative (not in catalog)
MPC855TZQ50D4
✅ Drop-In✓ In Stock
$19.5 / Unit
View Datasheet →MPC855TEZQ66D4
✅ Drop-In📋 Reference alternative (not in catalog)
MPC855TZQ66D4 Maximum Ratings & Electrical Characteristics
| Manufacturer | NXP Semiconductors (formerly Freescale) |
| Series | PowerQUICC, MPC8xx |
| Core Processor | MPC8xx |
| Core Count | 1 |
| Data Bus Width | 32-bit |
| Maximum Clock Frequency | 66 MHz |
| Operating Temperature | 0C to +95C |
| Package | 357-PBGA (25 mm x 25 mm) |
| Mounting Type | Surface Mount (BGA) |
| Integrated Ethernet | 10/100 Mbit/s Fast Ethernet MAC |
| Communications Module | CPM with SCC/SMC/UART, ATM, HDLC, PCMCIA support |
| Architecture | PowerPC (Power Architecture) |
| I/O Voltage | 3.3 V |
| RoHS Status | Non-compliant (legacy PBGA, SnPb balls) |
| Lifecycle Status | End of Life / Last Time Buy per NXP PCN |
| Sub-Family | MPC860 PowerQUICC derivative |
| Note | Designed for cost-effective 100 Mbps Ethernet access equipment |
MPC855TZQ66D4 357-pbga (25 mm x 25 mm) Pin Configuration Guide
Pin configuration for MPC855TZQ66D4 (357-pbga (25 mm x 25 mm) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for MPC855TZQ66D4.
Refer to the datasheet for full pin configuration.
Typical Applications
MPC855TZQ66D4 is suitable for 6 applications: SOHO Router / Broadband Gateway, xDSL Modem / Access Multiplexer Line Card, Industrial Serial-to-Ethernet Gateway, ISDN Router / PRI Gateway, VoIP Media Gateway (Legacy), Embedded Control Plane / Legacy Telecom.
SOHO Router / Broadband Gateway
The MPC855TZQ66D4 was purpose-built for low-cost broadband gateways and SOHO routers. Its 66 MHz MPC8xx core provides sufficient throughput for routing and NAT, while the integrated 10/100 Mbit/s Ethernet MAC removes the need for an external PHY-side controller. The dedicated CPM offloads PPPoE, TCP/IP, and ATM framing from the main CPU, freeing the core for packet forwarding. Placed as the main SoC on the mainboard with SDRAM, Flash, and a Fast Ethernet transceiver, it delivers 100 Mbps routing at consumer price points. Unlike later MPC85xx devices, it does not need an external TCAM but is limited to single-Ethernet-port designs.
Recommended
xDSL Modem / Access Multiplexer Line Card
ADSL and VDSL CPE historically used the MPC855T as the primary processor because the CPM handles ATM AAL5 segmentation/reassembly natively. The 66 MHz core drives PPPoA/PPPoE bridging and IP routing, while SCC channels provide the DSL framer interface and SMC channels serve UART debug consoles. With the 357-PBGA package, the device can be paired with an external DSL AFE and a 10/100 Ethernet PHY on a four-layer board. This part was a workhorse in early 2000s DSL deployments and remains in production equipment at telcos and ISPs.
Recommended
Industrial Serial-to-Ethernet Gateway
Industrial gateways converting RS-232/485 to Ethernet leverage the MPC855TZQ66D4 because the CPM provides multiple SCC/SMC channels running async or HDLC, while the 10/100 MAC handles Ethernet. The 0C to +95C operating range covers indoor factory environments, and the 357-PBGA supports 24/7 continuous operation. Typical designs use two SMCs for dual RS-485 ports and the FCC/FEC for Ethernet, with the main CPU running the Modbus/TCP or EtherNet/IP stack. Aging but reliable, this part remains deployed in industrial automation cabinets.
Recommended
ISDN Router / PRI Gateway
Legacy ISDN routers and PRI (E1/T1) gateways used the MPC855T because its HDLC controllers and SCC channels natively support ISDN's LAPD and Q.921 protocols. The CPM offloads D-channel handling, freeing the main CPU for call routing and voice gateway DSP coordination. With support for PCMCIA, developers could add Wi-Fi or modem cards via the PCMCIA host interface. The 66 MHz device easily routes multiple PRI lines and supports VoIP-side interworking with external DSP chips.
Recommended
VoIP Media Gateway (Legacy)
Early VoIP media gateways leveraged the MPC855TZQ66D4 to bridge PSTN T1/E1 lines to IP networks. The CPM's SCC channels handle T1/E1 framing, while the MPC8xx core runs RTP stacks and SIP signaling. The 100 Mbit/s Ethernet MAC aggregates VoIP traffic efficiently. Although modern designs use DSP + ARM SoCs, surviving MPC855T-based gateways are still in service at small PBX vendors. The part's long lifecycle status makes it useful for repair and refurbishment of installed base equipment.
Recommended
Embedded Control Plane / Legacy Telecom
The MPC855TZQ66D4 was used as a control-plane CPU in legacy central-office switches and multiplexer shelves where deterministic protocol handling was more important than raw CPU speed. The CPM processes ATM, HDLC, and SS7 signaling links concurrently with predictable latency, while the MPC8xx core runs the management and OAM stack. The 357-PBGA mounts on standard telecom backplane CPU cards. Because NXP has issued a Last Time Buy notice, control-plane designs are typically now migrating to MPC83xx/MPC85xx devices via life-extension programs.
Recommended
Recommended Products Summary
Engineering reference data for MPC855TZQ66D4 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | MPC860PCZQ66D4 | MPC860ENCZQ66D4 | MPC855TZQ50D4 | MPC855TEZQ66D4 |
|---|---|---|---|---|---|
| Brand | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors |
| Package | 357-PBGA (ZQ, 25x25 mm) | 357-PBGA (ZQ, 25x25 mm) | 357-PBGA (ZQ, 25x25 mm) | 357-PBGA (ZQ, 25x25 mm) | 357-PBGA (ZQ, 25x25 mm) |
| Core Clock Frequency | 66 MHz | 66 MHz | 66 MHz | 50 MHz | 66 MHz |
| Data Bus Width | 32-bit | 32-bit | 32-bit | 32-bit | 32-bit |
| Ethernet MAC | 10/100 Mbit/s Fast Ethernet | 10/100 Mbit/s Fast Ethernet | 10/100 Mbit/s Fast Ethernet | 10/100 Mbit/s Fast Ethernet | 10/100 Mbit/s Fast Ethernet |
| Number of SCC Channels | 1 SCC + 2 SMC | Multiple SCCs (more channels) | Multiple SCCs with additional HDLC | 1 SCC + 2 SMC (same) | 1 SCC + 2 SMC (same) |
| Operating Temperature | 0C to +95C | 0C to +95C | 0C to +95C | 0C to +95C | -40C to +95C (extended) |
| Core Architecture | MPC8xx (PowerPC) | MPC8xx (PowerPC) | MPC8xx (PowerPC) | MPC8xx (PowerPC) | MPC8xx (PowerPC) |
| Lifecycle Status | EOL / Last Time Buy | EOL / Last Time Buy | EOL / Last Time Buy | EOL / Last Time Buy | EOL / Last Time Buy |
Key Differentiators
- Single 10/100 Ethernet MAC keeps cost low for SOHO gateway designs (vs MPC860ENCZQ66D4)
- Standard 0C to +95C industrial operating range (vs MPC855TEZQ66D4)
- Same ZQ package as MPC860 family for legacy board reuse (vs MPC8313VRADDB)
Design Notes
Estimated: At an ambient of +70C inside a sealed SOHO router and a typical core power dissipation of approximately 2 W (66 MHz, Vcore 2.0 V, internal logic only), the 357-PBGA requires at least 5 thermal vias under the die flag and a continuous ground/power pour on inner PCB layers to keep junction below 105C. Without active cooling, do not place the BGA directly above or below heat-generating sources such as linear regulators.
The 357-PBGA demands a 4-layer PCB minimum with 0.5 oz copper outer layers and 1 oz inner power/ground planes. BGA land pattern must follow NXP's IPC-7351 PBGA-357 recommended footprint. Use ENIG finish for best solderability on legacy tin-lead ball variants; HASL SnPb is preferred for matching the original SAC-free ball metallurgy. Trace routing inside the BGA escape region must use microvia or 4-mil trace/space design rules.
Do not confuse the MPC855T (single-FEC Ethernet) with the MPC860T (dual-FEC Ethernet) or the MPC8555E (PowerQUICC III). The package suffix 'ZQ' specifically denotes the 25x25 mm 357-PBGA; other suffixes correspond to PBGA-357 with different ball mapping. Verify against the MPC855T Hardware Specification, not the MPC860 pinout, when laying out the board. Always check the silicon revision (Rev 1.0 vs 2.0) for errata that may affect PCMCIA and SCC timing.
The 66 MHz system bus radiates significant third-harmonic energy; place SDRAM as close as possible to the data/address bus group and use series termination resistors (22-33 ohm) on heavily-loaded address lines. For the MII Ethernet interface, route the MII_TXCLK and MII_RXCLK as length-matched 50-ohm transmission lines and keep the MII_DATA nibbles together. The CPM clock output should be sourced-followed if driving more than two SCC loads.
The MPC855TZQ66D4 requires a 2.0 V core supply and a 3.3 V I/O supply derived from the same input rail. Use a low-dropout regulator for the 2.0 V core capable of at least 800 mA peak; the device draws up to 1.5 A peak under worst-case internal clock gating. Decouple the core with 10 uF bulk tantalum plus 0.1 uF and 10 nF ceramics placed within 5 mm of each BGA power pin group.
Compliance Information
Verified Web Data from chipdig.com lists RoHS: No. Tin-lead solder balls in 357-PBGA. Reach, halogen-free, and conflict-minerals status not specified in provided data; marked unknown.
